Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5-12, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dai et al. U.S. PGPUB No. 2025/0183801 in view of Rahardjo et al. U.S. PGPUB No. 2011/0080151, in further view of Zhang et al. U.S. PGPUB No. 2017/0248996.
Per Claim 1, Dai discloses:
a computer system (computing device 100) comprising:
one or more integrated circuits (processor 160);
and a voltage regulator device (voltage regulator 170) including a hybrid phase circuit (Paragraph 38; Power stage circuit 140A represents a “hybrid phase circuit” as broadly claimed as it differs from the other power stage circuits 140B-140N since it can have a maximum output current lower than the other power stage circuits.) and a resistive component (Paragraph 52; resistor 306A) coupled to a load (Paragraph 50, Fig. 3; Vcore 316 illustrates an operating voltage of processor 160.),
wherein the hybrid phase circuit includes a heterogeneous power stage (Paragraph 31; “utilizing heterogenous power stage circuits that support different current maximums”) and a nonlinear inductive component coupled between the hybrid phase circuit and the resistive component and load (Paragraph 51 and Figure 3; Inductor 304A),
and the heterogeneous power stage is configured to provide a signal to the nonlinear inductive component (Paragraph 51, Figure 3; The transistors 308A/308B of power stage circuit 140A can be considered the “heterogenous power stage” that provides a signal to inductor 304A.),
wherein the hybrid phase circuit is configured to selectively operate in a first mode or a second mode depending on an amplitude of a current of the signal being less/more than a threshold amplitude and a first inductance of the nonlinear inductive component being greater/less than a first/second threshold inductance (Paragraph 49 discusses various threshold currents (e.g. 5A, 10A, or the like). Paragraph 53 discusses two different maximum output currents of the power stage circuits. Paragraphs 58-69 and Figure 4 discuss comparing a current value to a threshold current and determining which of two modes (single stage or multi-stage) the power stage circuit(s) will be operated in. Paragraph 51; Inductor 304A has an inductance that is higher than the inductance of inductor 304B, and example values of 330nH and 150nH are provided.),
and wherein the voltage regulator device is configured to provide a power supply signal having a regulated voltage to the one or more integrated circuits (Paragraph 46, Fig. 2; The supply signals 206A-N are provided to the processor 160.).
Dai does not specifically teach more than one threshold current.
However, Rahardjo similarly teaches a voltage regulator 110 comprising a plurality of power phases 114a-114n (Paragraph 20, Figure 1). Rahardjo further teaches a plurality of current demand threshold levels that can be used to configure the voltage regulator power stages to provide the required current to a load (Paragraphs 21 and 22).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Rahardjo’s multiple current thresholds within the system of Dai because it can reduce operational temperature of the phases and increase power efficiency of the voltage regulator (Rahardjo; Paragraph 25).
Dai does not specifically teach the voltage regulator comprising a capacitive component. Rahardjo teaches a capacitor 211/213, but they are located within the power stage 122 of the phase circuit 114a, and not outside of the phase circuit but resident to the voltage regulator.
However, Zhang teaches a voltage regulator phase 114 comprising a power stage 120 with a nonlinear inductor (Paragraphs 41 and 48), and further teaching an output filter, generally comprising a capacitor C (Paragraph 43, Figure 2).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement a capacitive element between the voltage regulator and the processor load of Dai, as taught by Zhang, because it helps to provide an output voltage with a constant amplitude (Zhang; Paragraph 43)
Per Claim 2, Dai discloses the computer system of claim 1, further comprising a voltage regulator (VR) controller (120) coupled to the voltage regulator device and configured to control an amplitude of the regulated voltage of the power supply signal provided by the voltage regulator device (Paragraph 37; “provide sensed current to the voltage regulator controller 120 for managing or balancing current supplied by each of the power stage circuits 140A-140N”).
Per Claim 5, Dai discloses the computer system of claim 2, wherein the hybrid phase circuit is a first phase circuit, the heterogeneous power stage is a first power stage, the nonlinear inductive component is a first nonlinear inductive component, and the signal provided by the first phase circuit is a first signal, and the voltage regulator device further comprises: one or more second phase circuits, each of the second phase circuits including a second nonlinear inductive component and a second power stage configured to provide a second signal to the second nonlinear inductive component, wherein the second nonlinear inductive component of each second phase circuit is coupled between the second power stage of the respective second phase circuit and the capacitive component; one or more third phase circuits, each of the third phase circuits including a third inductive component and a third power stage configured to provide a third signal to the third inductive component, wherein the third inductive component of each third phase circuit is coupled between the third power stage of the respective third phase circuit and the capacitive component (Figure 2; Dai discloses any number of “one or more second phase circuits”, each comprising non-linear inductive components 304 (power stage circuits 140B-140N)). Please refer to the rejection of claim 1 for detail on Zhang teaching the capacitive component.
Per Claim 6, Dai discloses the computer system of claim 5, wherein the VR controller is further configured to perform operations including: monitoring one or more parameters of the voltage regulator device; and controlling an operating mode of the voltage regulator device based on whether the one or more monitored parameters satisfy one or more criteria (Paragraphs 56-69, Figure 4; The criteria can be the threshold current determination of step 404.).
Per Claim 7, Dai discloses the computer system of claim 6, wherein the one or more parameters of the voltage regulator device include an amplitude of a current of the power supply signal provided by the voltage regulator device to the one or more integrated circuits (Paragraph 58, Fig. 4 numeral 404).
Per Claim 8, Dai discloses the computer system of claim 1, further comprising a printed circuit board, wherein the voltage regulator device and the one or more integrated circuits are attached to the printed circuit board, and wherein the voltage regulator device is electrically coupled to the one or more integrated circuits via the printed circuit board (Paragraph 36; “In some examples, the voltage regulator controller 120 may be a part of a system-on-a-chip and can be deployed along with the sensing circuits 180, the power stage circuits 140A through 140N, and other components (not shown in FIG. 1) of the computing device 100 on a single or multiple integrated circuits or chipsets.”).
Per Claim 9, Dai discloses the computer system of claim 1, wherein the one or more integrated circuits include a central processing unit (CPU), a graphics processing unit (GPU), and/or an accelerated processing unit (APU) (Paragraphs 35 and 41; Processor 160 can be a CPU or GPU.).
Per Claim 10, please refer to the above rejection of claim 1 as the voltage regulator device and all subsequent limitations are substantially similar and the rejection and mapping of limitations is equally applicable.
Per Claim 11, Dai discloses the voltage regulator device of claim 10, wherein the hybrid phase circuit and the capacitive component form a DC-to-DC converter (Paragraph 35; Computing device 100 can be a laptop, tablet, wearable computer, smartphone etc. Each of these are examples of portable devices that run on batteries (see Paragraphs 30 and 39). Therefore, the power conversion of Dai represents a DC-DC conversion.).
Per Claim 12, Zhang further teaches that the voltage regulator phases can comprise a driver stage 118 and a half-bridge power switching topology (Paragraph 40, Figure 2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement this topology within the power stage of Dai because switching topologies offer advantages over linear topologies, including higher efficiency and smaller size (Zhang; Paragraph 37).
Per Claim 16, Dai discloses the voltage regulator device of claim 10, wherein the hybrid phase circuit is a first phase circuit, the heterogeneous power stage is a first power stage, and the nonlinear inductive component is a first nonlinear inductive component, the voltage regulator device further comprising: one or more second phase circuits, each of the second phase circuits including a second power stage and a second nonlinear inductive component coupled between the respective second power stage and the capacitive component (Figure 2; Dai discloses any number of “one or more second phase circuits”, each comprising non-linear inductive components 304 (power stage circuits 140B-140N)). Please refer to the rejection of claim 1 for detail on Zhang teaching the capacitive component.
Per Claim 17, Dai discloses the voltage regulator device of claim 16, further comprising: one or more third phase circuits, each of the third phase circuits including a third power stage and a third inductive component coupled between the respective third power stage and the capacitive component (Figure 2; Dai discloses any number of “one or more second phase circuits”, each comprising non-linear inductive components 304 (power stage circuits 140B-140N)). Please refer to the rejection of claim 1 for detail on Zhang teaching the capacitive component.
Per Claim 18, please refer to the above rejection of claim 1 as the voltage regulator device and all subsequent limitations are substantially similar and the rejection and mapping of limitations is equally applicable.
Allowable Subject Matter
Claims 3, 13, 14, 15, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
- The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 distinguishes over Dai, Rahardjo, Zhang, and the prior art due to the time period limitations when considered in combination with the other limitations of this claim and the intervening claims.
Claims 13-15, 19, and 20 each distinguish over Dai, Rahardjo, Zhang, and the prior art due to the half-bridge and switch/duty cycle limitations when considered in combination with the other limitations of each of these claims and their intervening claims.
Claim 4 inherits the allowable subject matter of Claim 3.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights