DETAILED ACTION
Claims 1-11, 14-19 are amended. Claims 1-20 are pending.
Priority: 11/28/2023
Assignee: Samsung
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/21/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 9-10, 12-13, 17-18, 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698) and Yuan (8601223).
As per Claim 1, Talagala discloses a method (Talagala, [0012 - A disclosed method comprises generating an access data structure configured to indicate access characteristics of logical identifiers within a logical address space of a backing store, admitting data of the backing store into a cache based on access metrics of the logical identifiers]; [0042 – Fig. 1 shows system 100 which includes host 114 and storage device 102]) comprising:
receiving a request related to at least one of an operating system and an application (Talagala, [0249 – In Fig. 16, at step 1620, a request is received to admit data into the cache]; [0121 - The write program module 310 allows a user to customize the write data pipeline 106, implying relation to application/user]; [0093 - The write data pipeline 106 includes a packetizer 302 that receives a data or metadata segment to be written to non-volatile storage; The phrase 'receiving a request' serves as the gateway event that begins a communication sequence. The incoming request is the specific message that initiates the interaction between the sender/host and receiver/memory device. This interpretation is supported by the spec which recites in Para-0027, an Extended Berkeley Packet Filter/eBPF environment. It is well known that an eBPF environment uses XDP hooks. So when a packet hits an XDP hook, it represents the beginning of a communication]; [0140 - The storage clients 412 may include operating systems, hypervisors, database applications, server applications, etc.]);
wherein the request (Talagala, [0093 - A set of data such as a data structure is received from host 114 and is transmitted to the non-volatile storage device 102 in data segments streamed to the non-volatile storage device 102]) comprises an identifier identifying one of the operating system or the application (Talagala, [0093 – W.r.t. the write data pipeline 106, the metadata segment is part of a data structure such as an object]; [0095 - The header includes an object identifier or other data structure identifier and offset that indicate the data segment, object, data structure or data block from which the data packet was formed]; [0173 – In Fig. 6, logical identifier 632 and data length 634 are called source parameters 646]; [0167 - A storage client may request allocation of a particular logical identifier/LBA, implying a request related to an OS]; [0121 - The write program module 310 allows a user to customize the write data pipeline 106, implying a request related to an application request]);
determining that the request (Talagala, [Figs. 1-4]; [0167 - A storage client may request allocation of a particular logical identifier/LBA; Here the generation of a request targeting a specific LBA is a function of the OS layer or filesystem manager, making it an OS request]) is related to the operating system based on the identifier (Talagala, [0010 - an access metric of the logical identifier satisfying an admission criteria; The performance analysis module profiles metadata and evaluates the access metrics .i.e. frequency/location of a specific LBA. When these metrics satisfy the system's cache admission criteria, the controller considers the request identifier as OS related to determine its memory priority]; [0053 - The storage device 102 is a log structured file system such that there is no ‘fixed’ relationship to determine the mapping of the LBA to the PBA, but may be accessed by more than one client or file server 114/host such that the logical identifiers allocated to each client or file server 114 represents a large storage capacity; Here because the allocation request occurs in a multi-client environment, it requires a central authority like the OS to issue and coordinate the allocation to prevent corruption. Furthermore, the dynamic translation and mapping of floating LBAs to PBAs is a core function of the OS. Therefore, requesting an LBA/identifier allocation in this environment is a request related to the OS]);
determining a priority score for data corresponding to the request (Talagala, [0249 – In Fig. 16, step 1630 comprises determining an access metric of the data and a sequentiality metric of the data using access metadata, thereby determining a score/priority score; Access and sequentiality metrics are used to calculate a priority score that determines how urgently data is cached, fetched, or processed. Since the claim does not recite how the ‘priority score’ is determined, the citation is a valid interpretation]; [0198 – ‘Access metric’ of a logical identifier quantifies the access frequency]; [0009 - The sequentiality metric is based on previous access requests within a threshold logical proximity to the logical identifier]; [0244 – In Fig. 15A, plot 1500, point 1581, data having a high access metric is admitted into the cache even through the sequentiality metric indicates a sequential data access; This implies that High Access Frequency + Lower Sequentiality = High or Medium Priority score]);
writing the data to memory media (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM]; [0074 – buffers 222]) based on the priority score (Talagala, [0250 - Step 1640 comprises determining whether the data is suitable for admission to the cache]; [0251 - If the data satisfies the admission criteria/priority score of step 1640, then at next step 1650 the data is admitted into the cache]).
Surianarayanan further clarifies determining a priority score for the data as follows,
determining a priority score for data (Surianarayanan, [0068 – In Fig. 6, after steps 610, 620, in step 630, the storage device receives a priority identifier associated with a first communication stream. Then in step 635, the storage device determines if the priority identifier exceeds a predetermined priority threshold/H/M/L. The priority identifier is assigned to certain data being transmitted through the stream]; [0062 - Fig. 5 shows process 500 for managing a high priority data communication stream]) corresponding to the request (Surianarayanan, [0066 – In Fig. 6, step 610, establish communication streams between a host and a storage device 120]; [0033 - A device driver for storage device 120 is configured to provide storage services to a host client. The device driver maintains metadata 135, such as a logical to physical address mapping structure, to map logical addresses of the logical address space 134 to media storage locations on storage device 120]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the priority identifier of Surianarayanan into the cache profiling of Talagala for the benefit of assigning a priority to a data communication stream. Additional resources may be assigned to a data communication stream that has been assigned a specific priority. This priority may be assigned and communicated through the use of one or more priority indicators. These priority indicators can include binary, hexadecimal values, or any demarcating label or value (Surianarayanan, Para-0013).
Yuan clarifies determining the request being related to an OS based on the identifier, as follows,
determining that the request (Yuan, [Col. 8, lines 3-4 – In Fig. 10, step 1005, a memory access request is received]) is related to the operating system (Yuan, [Col. 8, lines 7-11 – In Fig. 10, after step 1010, in step 1015, if it is determined there is a valid non-contiguous PTE cached for the VA, e.g., a TLB hit, the PFN in the valid PTE and byte offset in the VA are used to access physical memory; The system's reliance on non-contiguous translation structure suggests the access request is related to the OS. Furthermore, when the valid PTE from the TLB is used to access physical memory, the system evaluates cached attribute flags. If the valid PTE contains a privileged/admin flag, it further implies that the access request is related to the OS]) based on the identifier (Yuan, [Col. 8, lines 5-8 – In Fig. 10, step 1010, it is determined if a valid non-contiguous PTE is cached in a TLB for the virtual address/VA/identifier contained in the memory access request]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE includes a corresponding physical address of data and/or instructions in primary/volatile or secondary/NVM. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 2, the rejection of claim 1 is incorporated, and Talagala discloses,
wherein the data is first data (Talagala, [Fig. 16: step 1620, receive request to admit data into cache]);
the priority score is a first score (Talagala, [0249 – In Fig. 16, step 1630 comprises determining an access metric/access frequency of the data and a sequentiality metric/access pattern of the data using access metadata, thereby determining a priority score]; [Fig. 15A: point 1581, Medium Priority Score]);
wherein the computer implemented method further comprises:
determining that a second request is related to an application (Talagala, [Fig. 1: driver 118 is an API to translate commands]; [0049 – In Fig. 1, driver 118, has a storage interface connection to a file system and allocation done in the file system/file server is offloaded to storage device 102]; [0121 - A user customizes the write data pipeline 106 based on an application; Here, for a user to ‘customize’ a write data pipeline, they interact with a User Interface/UI, a configuration file, or API provided by an application. When the user finalizes their customized selections, e.g., file transfer/write data, setting block sizes, choosing encryption options, defining a cache policy etc., the application transmits these selections to the storage controller 104. Sending these custom parameters helps the storage controller 104 determine that the request is sent by the application]);
determining a second score for the data related to the second request, wherein the data related to the second request is second data (Talagala, [0218 – In Fig. 11, step 1120 comprises caching the data using storage module 430; Since caching data occurs in response to a write request from a host application, it is valid to interpret that the write/second request is an application-related request]; [0220 – In Fig. 11, step 1140 determines whether to admit data/second data of a logical identifier]; [Fig. 11: step 1140-Admit data of logical identifier? No; This implies that second data is not stored in the memory media]; [0221 – In Fig. 11, step 1140 comprises determining whether to admit the data as ‘low-value’ data. If the access metric of a logical identifier does not satisfy the access threshold, the data is admitted as ‘low-value’ data. The data may be admitted as low-value data in response to the access metric satisfying a lower access threshold, thereby implying determining a second priority score]);
writing the second data to storage media based on the second score (Talagala, [0221 - The low-value data is marked/written on the non-volatile storage media 410]).
Yuan clarifies the second request is related to an application as follows,
determining that a second request is related to an application (Yuan, [Col. 1, lines 35-36 - The application utilizes virtual addressing to access instructions and data]; [Col. 1-2, lines 65-67,lines 2-12 - In Fig. 1, upon receiving a virtual address, TLB 140 is accessed to determine if a mapping between the virtual address 110 and the physical address 120 has been cached. If TLB hit/yes, the physical address 120 is output from TLB 140. If not, the page table data structure is walked to translate the virtual address 110 to a physical address 120. The page table index in the virtual address 110 is used to index the appropriate page table specified in the given PDE to obtain the physical address 120 of the page containing the data; It is well known that a page table walk is performed because the application requested a virtual address that was not in the TLB cache/TLB miss. This implies that the second request is related to an application]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE includes a corresponding physical address of data and/or instructions in primary/volatile or secondary/NVM. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 4, the rejection of claim 2 is incorporated, and Talagala discloses,
the first data and second data use a cache comprising at least one of a type (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory of type, DRAM 230 and SRAM 232]) and a priority level (Talagala, [0265 – Eviction criteria]; [0199 - Low-value data may be evicted from the cache before other, higher-value data, e.g., data that satisfied the admission criteria. Accordingly, low-value data is marked within the cache]).
As per Claim 5, the rejection of claim 2 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
the data comprises at least one page table (Yuan, [Col. 5, lines 44-45 – Figs. 5-6 show a page table]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 9, Talagala discloses a system (Talagala, [0042 - Fig. 1 shows system 100 comprising host 114 and storage device 102]) comprising:
a host device (Talagala, [Fig. 1: host 114]; [Fig. 4: host 401]) comprising a one or more circuits configured to associate virtual addresses to physical addresses (Talagala, [0049 – In Fig. 1, driver 118 or storage interface 116 is an API and acts to translate commands and other data to a form suitable to be sent to storage controller 104]) on a memory device (Talagala, [Fig. 1: storage device 102]; [Fig. 2: NVM storage device 102]);
the memory device (Talagala, [Figs. 1-2: storage device 102]) comprising storage media (Talagala, [Fig. 1: NVM media 110]; [Fig. 4: NVM media 410]) and memory media (Talagala, [0087 – DRAM]; [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM and SRAM]);
wherein the memory device is used as expanded memory on the host device (Talagala, [0153 - The availability of large, contiguous ranges in the logical address space is enabled by the large address space/64-bit, presented by the storage module 430 in host 401]; [0153 - The storage module 430 is configured to allocate large, contiguous ranges within the logical address space 432 and to defer assigning physical storage locations on the non-volatile storage device 402 to the logical identifiers until necessary]; [0224 - A storage client 412 operates on relatively large, contiguous data segments. In response, the pre-admission access threshold may be set lower than the access threshold to bias the cache admission module 444 towards pre-admitting contiguous data segments]).
To perform the claimed step of ‘determining’, the request must carry an identifier. Evaluating this identifier to handle the request functionally satisfies the claimed limitation of ‘determining that the request is related to the operating system’. Consequently, the limitations are similar to claim 1 and therefore the same mappings are incorporated.
As per Claim 10, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 12, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 13, it is similar to claims 5,9 and therefore the same mappings are incorporated.
As per Claim 17, Talagala discloses a device (Talagala, [0042 - Fig. 1 shows system 100 comprising a non-volatile storage device 102]; [0045 - The storage device 102 provides non-volatile storage for host 114]) comprising:
memory media (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM 230 and SRAM 232]);
storage media (Talagala, [Fig. 1: NVM storage media 110, Fig. 4: NVM storage media 410]);
at least one circuit (Talagala, [Figs. 2-3]) configured to perform one or more operations (Talagala, [0044 – In Fig. 1, storage device 102 performs data storage operations such as reads, writes, erases, etc.]) comprising:
receiving a data structure (Talagala, [0093 - A set of data such as a data structure is received from host 114 and is transmitted to the non-volatile storage device 102]) related to the operating system (Talagala, [0093 - The write data pipeline 106 includes a packetizer 302 that receives a data structure to be written to non-volatile storage; The data or metadata segment is part of a data structure]; [0249 – In Fig. 16, at step 1620, a request is received to admit data into the cache]);
Yuan clarifies the ‘data structure’ as follows,
receiving a data structure (Yuan, [Col. 8, lines 3-4 – In Fig. 10, step 1005, a memory access request is received]; [Col. 8, lines 5-8 – In Fig. 10, step 1010, it is determined if a valid non-contiguous PTE is cached in a TLB for the virtual address/VA contained in the memory access request]) related to the operating system (Yuan, [Col. 8, lines 7-11 – In Fig. 10, after step 1010, in step 1015, if it is determined there is a valid non-contiguous PTE cached for the VA, e.g., a TLB hit, the PFN in the valid PTE and byte offset in the VA are used to access physical memory; The system's reliance on non-contiguous translation structure suggests the data structure in the request is related to the OS. Furthermore, when the valid PTE from the TLB is used to access physical memory, the system evaluates cached attribute flags. If the valid PTE contains a privileged/admin flag, it further implies that the data structure is related to the OS]),
The remaining limitations are similar to claims 1, 9 and therefore the same mappings are incorporated.
As per Claim 18, the rejection of claim 17 is incorporated, and Talagala discloses,
wherein the data structure is first data (Talagala, [Fig. 16: step 1620, receive request to admit data/data structure/first data into cache]);
wherein at least one circuit (Talagala, [Figs. 2-3]) configured to perform one or more operations (Talagala, [0044 – In Fig. 1, storage device 102 performs data storage operations such as reads, writes, erases, etc.]) comprising:
receiving second data related to an ([See 112(a), 112(b)]) application (Talagala, [Figs. 1-4]; [0121 - A user customizes the write data pipeline 106 based on an application]; [0139 - an user-space application]; [0049 – In Fig. 1, driver 118 or storage interface 116, is an API/application program interface and acts to translate commands and other data to a form suitable to be sent to storage controller 104]; [0218 – In Fig. 11, step 1120 comprises caching data corresponding to a backing store 460 on NVM storage media 410]; [0219 – In Fig. 11, step 1130 comprises maintaining access metadata pertaining to data accesses within the logical address space]);
determining a second score for the second data (Talagala, [0220 – In Fig. 11, step 1140 determines whether to admit data of a logical identifier and determining an access metric of the logical identifier]; [0221 - Step 1140 comprises determining whether to admit the data as ‘low-value’ data. If the access metric of a logical identifier does not satisfy the access threshold it may be admitted as ‘low-value’ data]);
comparing the first score (Talagala, [Fig. 16]; [0249 – Fig. 16, step 1630 comprises determining an access metric of the data and a sequentiality metric of the data using access metadata]; [Satisfy admission criteria? Yes]; [0250 - The comparison of step 1640 may be dynamic, according to the values of the access metric and/or the sequentiality metric determined at step 1630]) and the second score (Talagala, [Fig. 11]; [0221 - If the access metric of a logical identifier does not satisfy the access threshold it may be admitted as ‘low-value’ data; Since the claim does not recite how the comparison is done, the citation is a valid interpretation]);
writing the second data to the storage media based on the second score (Talagala, [0222 – In Fig. 11, step 1150 comprises storing the data on a non-volatile storage device]).
The remaining limitations are similar to claims 1-2 and therefore the same mappings are incorporated.
As per Claim 20, it is similar to claims 1,2,4 and therefore the same mappings are incorporated.
Claims 3, 11, 19 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698), Yuan (8601223) and Ballapuram et al (20220229778).
As per Claim 3, the rejection of claim 2 is incorporated, and Talagala, Surianarayanan, Yuan disclose cache profiling.
Ballapuram further discloses,
wherein the first data uses a first cache (Ballapuram, [0013 - The device switches the operating mode of a region of the volatile memory from the scratchpad mode to the cache mode, thereby decreasing the size of the scratchpad portion]);
the second data uses a second cache (Ballapuram, [0013 - The device switches the operating mode of a region of the volatile memory from the cache mode to the scratchpad mode, thereby increasing the size of the scratchpad portion]);
the first cache (Ballapuram, [Fig. 5: Operating mode=cache mode? Yes, step 515-Power up associated NVM section, step 520-operation portion in cache mode]; [0101 - At step 515, the section of the NVM associated with the portion is powered up. For example, the device may power up the Way 0 section so that eviction procedures and fill procedures are performed for the portion during operation in the cache mode]) applies a different cache replacement policy than the second cache (Ballapuram, [Fig. 4: Operating mode=scratchpad mode? Yes, step 415-Perform eviction procedures, step 420-Power down associated NVM section, step 430-operate portion in scratchpad mode]; [0090 - At step 415, eviction procedures are performed. For example, the device performs eviction procedures for the Way 0 portion. The eviction procedures are performed as part of the cache mode and before the Way 0 portion is operated in the scratchpad mode at 420]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scratchpad mode of Ballapuram into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of having a device/SSD operate a portion of the volatile memory in a scratchpad mode so that certain requests from the host can be satisfied with deterministic latency. In the scratchpad mode, requests that implicate the portion may be satisfied exclusively by the volatile memory and non-deterministic latency operations used in the cache mode may be avoided, thereby allowing the device to operate according to deterministic latency (Ballapuram, 0013).
As per Claim 11, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 19, it is similar to claim 3 and therefore the same mappings are incorporated.
Claims 6-8, 14-16 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698), Yuan (8601223) and Haswell (20200183855).
As per Claim 6, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
the one or more entries corresponds to data accessed above a threshold (Yuan, [Col. 5, lines 54-60 - The attributes 620 include one or more contiguous bits 630. If a plurality of contiguous virtual pages 510 are mapped to a plurality of contiguous physical pages 520, the frame address 610 of each corresponding PTE, e.g., PTE 2,3,4,5 may be the physical page number of the base physical page number, lowest address—0020 and the contiguous bits 630 are set to the number of contiguous pages, e.g. 4; It is well known that storing data in contiguous pages is directly related to a high data access rate because it exploits the principle of spatial locality]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
the computer-implemented method further comprises writing data corresponding to the data accessed above a threshold from storage media to the memory media (Haswell, [0039,0040,0041 – In Fig. 3, step 351, performs a host read by performing an L2P Update table lookup at step 352. If the entry is ‘not found’, an L2P Table Cache lookup is performed at step 353. If the entry is not found in the L2P Update portion or the L2P Table Cache, a load region operation is performed at step 354, which loads a L2P region/contiguous/above threshold stored on the NVM/storage media to the memory media]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 7, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
the one or more entries corresponds to data accessed above a threshold (Yuan, [Col. 5, lines 54-60 - The attributes 620 include one or more contiguous bits 630. If a plurality of contiguous virtual pages 510 are mapped to a plurality of contiguous physical pages 520, the frame address 610 of each corresponding PTE, e.g., PTE 2,3,4,5 may be the physical page number of the base physical page number, lowest address—0020 and the contiguous bits 630 are set to the number of contiguous pages, e.g. 4; It is well known that storing data in contiguous pages is directly related to a high data access rate because it exploits the principle of spatial locality]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
the computer implemented method further comprises storing data corresponding to the data accessed above a threshold in the memory media (Haswell, [0042 – In Fig. 4, at step 460 performing a write operation of the data from the host]; [0043 - At step 462, a determination is made as to whether the L2P Table cache contains the required region/contiguous/above threshold addressing the logical address of the host written data, step 462:No]; [0044 - At step 463, a determination is made as to whether the L2P Update portion contains enough available space to receive an updated TU/translation unit resulting from the host write operation. If yes, then at step 468 the entry is inserted into the L2P Update table, in memory media]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 8, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
the one or more entries corresponds to data accessed below a threshold (Yuan, [Col. 5, lines 66-67 - The contiguous bits directly specify the number of contiguous pages. But, a bit value of ‘0’ indicates that the page is not contiguous with another page, thereby implying access below a threshold]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
the computer implemented method further comprises modifying data corresponding to the data accessed below a threshold from the memory media to storage media (Haswell, [Fig. 4: steps 461-Host write, step 462-L2P Table cache has required region?Yes, step 466-Update region, step 467-Flush region to NAND]; [0046 – In Fig. 4, after steps 461, 462, at step 466, the L2P Table cache/volatile, is updated with all relevant entries for that region in the L2P Update table in addition to the update required for this host write operation. Once it has been updated/modified the region is written back to the L2P Table stored in NVM/storage media at step 467]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 14, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 15, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 8 and therefore the same mappings are incorporated.
Response to Arguments
The Applicant's arguments filed on July 21, 2026 have been fully considered, but they are not persuasive.
Applicant argues: ‘Talagala in view of Surianarayanan ….does not teach …..at least, "receiving a request related to ….one of an operating system and an application, wherein the request comprises an identifier identifying one of the ….or the application; [and] determining that the request is related to the operating system based on the identifier" as recited in claim 1’. (Rem, Pg. 12)
Response: Please see O/A.
Examiner Notes:
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
1.’Data storage device employing caching groups defined by write counts of data blocks and operating method thereof’, US20220164292A1, SK Hynix- An operating method of a data storage device includes steps of: checking a write count of each of a plurality of data blocks in a first memory apparatus, setting, as a first bit value, a bit value corresponding to each start position of consecutive data blocks having the same write count as each other, in a bitmap having the same size as the number of the plurality of data blocks, forming a plurality of caching groups each including one or more data blocks by using the first bit value and caching data stored in the first memory apparatus to a second memory apparatus on a caching group basis.
2.’Non-volatile storage addressing using multiple tables’, US20130198439A1, Hitachi - The control unit is characterized by storing in the first memory the first table,LPT for translating a logical address of data of the first memory to a physical address, storing in the second memory a cache of the first table,LPT-C and a second table, an area table, for showing where in the first memory the first table is stored, and further storing in the second table multiple addresses, of the first table in the first memory.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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