DETAILED ACTION
Claims 1-2, 6-10, 14-20 are amended. Claims 1-20 are pending.
Priority: 11/28/2023
Assignee: Samsung
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Note: In the Remarks, the applicant does not mention the relevant specification paragraphs that recite the amendments.
Claim(s) 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1-2,9-10,17-18,20 are rejected for reciting a limitation that is unclear, vague and indefinite.
Amended Claim 1 recites, ‘determining that data….is related to an operating system’. The spec does not recite this limitation.
Spec, Para-0005 recites, ‘determining that data is related to an operation of an operating system’.
Reciting ‘data related to an operating system’ is broad and focuses mostly on static data because it includes all files, configuration data, system binaries, kernel binary, registry keys, system libraries, etc., that define the OS.
But ‘data related to an operation of an operating system’ is narrow/functional because it focuses on dynamic, active, runtime data generated by OS operations like process scheduling, I/O handling, memory management (allocation/deallocation), file system management (creating, moving, deleting files, directories etc.). This is data that changes based on what the system is currently doing.
In essence, the recitations are not equivalent.
Amended Claim 2 recites, ‘determining that second data is related to an application’. The spec does not recite this limitation.
But spec, Para-0005 recites, ‘determining that second data is related to an operation of an application’.
Reciting ‘related to an application’ is broad, static data that belongs to an application. While ‘related to an operation of an application’ is about action and function. It is a more precise/narrow, functional data that is actively being used to perform a specific action, process, or task within an application. Therefore the recitations are not equivalent.
The limitations fail to clearly define the scope of the disclosure and can lead to multiple interpretations. Hence the amended limitations are indefinite. Hence claims 1-2,9-10,17-18,20 are rejected for reciting limitations that are unclear, vague and indefinite.
Note: This issue was mentioned in the previous 112(b). But the amendments and arguments do not resolve the issue and instead create a 112(a) issue. Hence the rejection has been clarified and maintained.
When claims are amended, they must still be supported by the original disclosure.
2.Amended Claim 2 is rejected for reciting a limitation that is unclear, vague, incorrect and indefinite.
Amended Claim 2 recites, ‘wherein….method…comprises:
determining that second data is related to an application’.
The claimed ‘second data’ is not received. But spec, Para-0006 recites, ‘receiving second data related to (an operation of) an application’.
Since ‘second data’ is not explicitly received, the recitation, ‘determining that second data is related to an application’, is indefinite. In addition, the limitation, ‘determining a second score for the second data’, is also indefinite. Hence claim 2 is rejected.
3.Claims 3-4, 11-12, 20 are rejected for reciting limitations that are unclear, ambiguous and indefinite.
Claims 3-4 have the same parent claim (claim 2). And Claim 3 recites, ‘wherein the first data uses a first cache’, ‘wherein the second data uses a second cache’.
But Claim 4 recites, ‘wherein the first data and second data use a cache comprising at….a type and a priority level’.
Claim 3 requires two distinct caches. But Claim 4 uses the term ‘a cache’, which usually means ‘one or more’. However by reciting ‘first data and second data use a cache’, the recitation allows for a single, shared cache, unlike Claim 3.
A single shared cache differentiated by type/priority (logically partitioned) is similar to two distinct (physically separate) caches, in function. The claims do not recite how they are different.
As recited, the limitations fail to clearly define the scope of the claims and can lead to multiple interpretations. Hence claims 3-4 are rejected. Claims 11-12,20 have the same issue.
Note: This issue was mentioned in the previous O/A, but it is unresolved. Hence the rejection has been clarified and maintained.
4.Amended Claims 1-2,9-10,17-18 are rejected for reciting limitations that are unclear, ambiguous and indefinite.
Amended Claim 1 clarifies the steps of writing data to memory media as follows: ‘receiving a request….;determining that data….is related to OS….;
determining a priority score….;writing the data to memory media…..’.
However Amended Claim 9 recites: ‘receiving data related to an operating system….;determining a priority score….;writing the data to the memory media….’.
As recited, in Amended Claim 9 it is unclear if the first limitation, ‘receiving data related to an operating system’, inherently includes the first two limitations of claim 1 namely, ‘receiving a request….;determining that data….is related to OS….;’.
Since the limitations do not clearly define the scope of the claims and are inconsistent with the spec, they are indefinite.
Note: This issue was previously indicated. Since the present amendments change the scope of the claims, the rejection has been clarified and maintained.
5.Amended Claims 1-2,9-10,17-18 are rejected for reciting limitations that are unclear, inconsistent and indefinite.
Amended Claim 1 recites, ‘writing the data to memory media based on the priority score’. And Amended Claim 2 recites, ‘writing the second data to storage media based on the second score’.
The spec does not recite these limitations.
As recited, ‘second score’ is undefined. Hence it is unclear what ‘second score’ means.
The spec does not recite writing to memory media or storage media, based on different scores. Since the limitations do not clearly define the scope of claims 1-2 and are inconsistent with the spec, they are indefinite. Claims 9-10,17-18 have the same issue.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Note: In the Remarks, the applicant does not mention the relevant specification paragraphs that recite the amendments.
Claim(s) 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Amended Claims 1-2,9-10,17-20 are rejected for reciting limitations that are unsupported by the spec.
Amended claim 1 recites, ‘receiving a request related to at least one of an operating system and an application’.
Nowhere does the spec recite this limitation. Spec, Para-0050 recites, ‘a storage device may receive a memory request’. And Para-0006 recites, ‘receiving data related to an operation of an operating system’. And Para-0006 also recites, ‘receiving second data related to an operation of an application’.
As per the spec, the request is not related to the (operation of the) OS and the (operation of the) application. It’s the data that is related to the (operation of the) OS and the (operation of the) application. So Claim 1 recites new matter.
Claim 1 further recites, ‘determining that data ….is related to the operating system’. The spec does not recite this limitation. Spec, Fig. 10, Para-0005 recites, ‘determining that data is related to an operation of an operating system’.
Amended Claim 2 recites, ‘determining that second data is related to an application’. But Para-0005 recites, ‘determining that second data is related to an operation of an application’.
‘Related to an OS’ is not equivalent to ‘related to an operation of an OS’. Similarly, ‘related to an application’ is not equivalent to ‘related to an operation of an application’. Please also see 112(b).
The limitations encompass subject matter not described in the spec. In other words, the spec fails to support the scope of the limitations.
Amended Claims 9-10, 17-20 also have the same issue. Claims 1-2, 9-10, 17-18, 20 recite new matter, and are rejected for reciting limitations unsupported by the spec.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 9-10, 12-13, 17-18, 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698) and Yuan (8601223).
As per Claim 1, Talagala discloses a method (Talagala, [0012 - A disclosed method comprises generating an access data structure configured to indicate access characteristics of logical identifiers within a logical address space of a backing store, admitting data of the backing store into a cache based on access metrics of the logical identifiers]; [0042 – Fig. 1 shows system 100 which includes host 114 and storage device 102]) comprising:
receiving a request related to at least one of an ([See 112(a)]) operating system and an application (Talagala, [0249 – In Fig. 16, at step 1620, a request is received to admit data into the cache]);
determining that data corresponding to the request (Talagala, [Figs. 1-4]; [0167 - A storage client may request allocation of a particular logical identifier. If the index 504 comprises an entry 505 that includes the requested logical identifier, the logical identifier associated with the request may be identified as being already allocated. If the logical identifier is not in the index, it may be allocated to the requester by creating a new entry 505/result in the index 504; Per Para-0140 the storage client can be an OS, and the allocation is an operation of the OS. Since the logical identifier/data is used to produce a result in the allocation operation, it implies determining that the ‘logical identifier’/data is related to an (operation of) OS]; [0159 - Fig. 5 shows storage metadata where a forward index 504 maintains allocations of the logical address space of storage device 102/SSD]) is related to the ([See 112(b)]) operating system (Talagala, [0140 – In Fig. 4, host 401 comprises storage clients 412 that include operating systems, virtual operating systems such as guest operating systems, hypervisors, etc., thereby implying determining that data is related with an OS]);
determining a priority score for the data (Talagala, [0249 – In Fig. 16, step 1630 comprises determining an access metric of the data and a sequentiality metric of the data using access metadata, thereby determining a score/priority score; Access and sequentiality metrics are used to calculate a priority score that determines how urgently data is cached, fetched, or processed. Since the claim does not recite how the ‘priority score’ is determined, the citation is a valid interpretation]; [0198 – ‘Access metric’ of a logical identifier quantifies the access frequency]; [0009 - The sequentiality metric is based on previous access requests within a threshold logical proximity to the logical identifier]; [0244 – In Fig. 15A, plot 1500, point 1581, data having a high access metric is admitted into the cache even through the sequentiality metric indicates a sequential data access; This implies that High Access Frequency + Lower Sequentiality = High or Medium Priority score]);
writing the data to memory media (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM]; [0074 – buffers 222]) based on the priority score (Talagala, [0250 - Step 1640 comprises determining whether the data is suitable for admission to the cache]; [0251 - If the data satisfies the admission criteria/priority score of step 1640, then at next step 1650 the data is admitted into the cache]).
Surianarayanan further clarifies determining a priority score for the data as follows,
determining a priority score for the data (Surianarayanan, [0068 – In Fig. 6, after steps 610, 620, in step 630, the storage device receives a priority identifier associated with a first communication stream. Once the priority identifier/score is received, in step 635, the storage device determines if the priority identifier exceeds a predetermined priority threshold/H/M/L]; [0062 - Fig. 5 shows process 500 for managing a high priority data communication stream]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the priority identifier of Surianarayanan into the cache profiling of Talagala for the benefit of assigning a priority to a data communication stream. Additional resources may be assigned to a data communication stream that has been assigned a specific priority. This priority may be assigned and communicated through the use of one or more priority indicators. These priority indicators can include binary, hexadecimal values, or any demarcating label or value (Surianarayanan, Para-0013).
Yuan clarifies determining the data corresponding to the request being related to an OS, as follows,
determining that data corresponding to the request (Yuan, [Col. 8, lines 3-4 – In Fig. 10, step 1005, a memory access request is received]) is related to (Yuan, [Col. 8, lines 5-8 – In Fig. 10, step 1010, it is determined if a valid non-contiguous PTE is cached in a TLB for the virtual address contained in the memory access request; In Fig. 10, translating a virtual address to a physical address is performed by the memory management unit 480, which is an OS related operation]) the operating system (Yuan, [Col. 8, lines 12-25 – In Fig. 10, after step 1020, steps 1025,1030 determine TLB hit or TLB miss and corresponding actions]; [Col. 6-7, lines 59-67,lines 1-7 – In Fig. 8, step 810 includes determining if a set of N contiguous pages in a virtual address space are mapped to a set of N contiguous pages in a physical address space. At step 840, the generated PTEs are stored in a page table, thereby implying that the data in the request is related to the OS]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE includes a corresponding physical address of data and/or instructions in primary/volatile or secondary/NVM. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 2, the rejection of claim 1 is incorporated, and Talagala discloses,
the data is first data (Talagala, [Fig. 16: step 1620, receive request to admit data into cache]);
the priority score is a first score (Talagala, [0249 – In Fig. 16, step 1630 comprises determining an access metric/access frequency of the data and a sequentiality metric/access pattern of the data using access metadata, thereby determining a priority score]; [Fig. 15A: point 1581, Medium Priority Score]);
wherein the method further comprises:
determining that second data ([See 112(b)]) is related to ([See 112(a), See 112(b)]) an application (Talagala, [Figs. 1-4]; [0121 - A user customizes the write data pipeline 106 based on an application]; [0049 – In Fig. 1, driver 118 or storage interface 116, is an API/application program interface and acts to translate commands and other data to a form suitable to be sent to storage controller 104]; [0218 – In Fig. 11, step 1120 comprises caching data corresponding to a backing store 460 on NVM storage media 410]; [0219 – In Fig. 11, step 1130 comprises maintaining access metadata pertaining to data accesses within the logical address space]);
determining a second score for the second data (Talagala, [0220 – In Fig. 11, step 1140 determines whether to admit data of a logical identifier]; [Fig. 11: step 1140-Admit data of logical identifier? No; This implies that second data is not stored in the memory media]; [0221 – In Fig. 11, step 1140 comprises determining whether to admit the data as ‘low-value’ data. If the access metric of a logical identifier does not satisfy the access threshold, the data is admitted as ‘low-value’ data. The data may be admitted as low-value data in response to the access metric satisfying a lower access threshold; Since the spec does not disclose how ‘second score’ is determined, the citation is a valid interpretation]);
writing the second data to storage media based on the ([See 112(b)]) second score (Talagala, [0221 - The low-value data is marked/written on the non-volatile storage media 410]).
Yuan clarifies the second data related to an application as follows,
determining that second data is related to an application (Yuan, [Col. 1, lines 35-36 - The application utilizes virtual addressing to access instructions and data]; [Col. 1-2, lines 65-67,lines 2-12 - In Fig. 1, upon receiving a virtual address, TLB 140 is accessed to determine if a mapping between the virtual address 110 and the physical address 120 has been cached. If TLB hit/yes, the physical address 120 is output from TLB 140. If not, the page table data structure is walked to translate the virtual address 110 to a physical address 120. The page table index in the virtual address 110 is used to index the appropriate page table specified in the given PDE to obtain the physical address 120 of the page containing the data]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE includes a corresponding physical address of data and/or instructions in primary/volatile or secondary/NVM. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 4, the rejection of claim 2 is incorporated, and Talagala discloses,
the first data and second data use a cache comprising at least one of a type (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory of type, DRAM 230 and SRAM 232]) and a priority level (Talagala, [0265 – Eviction criteria]; [0199 - Low-value data may be evicted from the cache before other, higher-value data, e.g., data that satisfied the admission criteria. Accordingly, low-value data is marked within the cache]; [See 112(b)]).
As per Claim 5, the rejection of claim 2 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
the data comprises at least one page table (Yuan, [Col. 5, lines 44-45 – Figs. 5-6 show a page table]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
As per Claim 9, Talagala discloses a system (Talagala, [0042 - Fig. 1 shows system 100 comprising host 114 and storage device 102]) comprising:
a host device (Talagala, [Fig. 1: host 114]; [Fig. 4: host 401]) comprising a one or more circuits configured to associate virtual addresses to physical addresses (Talagala, [0049 – In Fig. 1, driver 118 or storage interface 116 is an API and acts to translate commands and other data to a form suitable to be sent to storage controller 104]) on a memory device (Talagala, [Fig. 1: storage device 102]; [Fig. 2: NVM storage device 102]);
the memory device (Talagala, [Figs. 1-2: storage device 102]) comprising storage media (Talagala, [Fig. 1: NVM media 110]; [Fig. 4: NVM media 410]) and memory media (Talagala, [0087 – DRAM]; [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM and SRAM]);
wherein the memory device is used as expanded memory on the host device (Talagala, [0153 - The availability of large, contiguous ranges in the logical address space is enabled by the large address space/64-bit, presented by the storage module 430 in host 401]; [0153 - The storage module 430 is configured to allocate large, contiguous ranges within the logical address space 432 and to defer assigning physical storage locations on the non-volatile storage device 402 to the logical identifiers until necessary]; [0224 - A storage client 412 operates on relatively large, contiguous data segments. In response, the pre-admission access threshold may be set lower than the access threshold to bias the cache admission module 444 towards pre-admitting contiguous data segments]).
The remaining limitations are similar to claim 1 and therefore the same mappings are incorporated.
As per Claim 10, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 12, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 13, it is similar to claims 5,9 and therefore the same mappings are incorporated.
As per Claim 17, Talagala discloses a device (Talagala, [0042 - Fig. 1 shows system 100 comprising a non-volatile storage device 102]; [0045 - The storage device 102 provides non-volatile storage for host 114]) comprising:
memory media (Talagala, [0087 – In Fig. 2, memory controller 228 controls volatile memory such as DRAM 230 and SRAM 232]);
storage media (Talagala, [Fig. 1: NVM storage media 110, Fig. 4: NVM storage media 410]);
at least one circuit (Talagala, [Figs. 2-3]) configured to perform one or more operations (Talagala, [0044 – In Fig. 1, storage device 102 performs data storage operations such as reads, writes, erases, etc.]) comprising:
receiving a data structure (Talagala, [0093 - A set of data such as a data structure is received from host 114 and is transmitted to the non-volatile storage device 102/SSD]) related to an ([See 112(a), 112(b)]) operating system (Talagala, [0227 - In Fig. 16, at step 1620, receiving a request to admit data into cache, thereby implying that the request includes the data structure]; [0157 - Storage clients 412 access storage module interface 436 to request logical ranges the logical address space 432]; [0140 – In Fig. 4, host 401 comprises storage clients 412 that include operating systems, virtual operating systems such as guest operating systems, hypervisors, etc., thereby implying that data is related with operation of an OS]);
The remaining limitations are similar to claims 1,9 and therefore the same mappings are incorporated.
As per Claim 18, the rejection of claim 17 is incorporated, and Talagala discloses,
wherein the data structure is first data (Talagala, [Fig. 16: step 1620, receive request to admit data/data structure/first data into cache]);
wherein at least one circuit (Talagala, [Figs. 2-3]) configured to perform one or more operations (Talagala, [0044 – In Fig. 1, storage device 102 performs data storage operations such as reads, writes, erases, etc.]) comprising:
receiving second data related to an ([See 112(a), 112(b)]) application (Talagala, [Figs. 1-4]; [0121 - A user customizes the write data pipeline 106 based on an application]; [0139 - an user-space application]; [0049 – In Fig. 1, driver 118 or storage interface 116, is an API/application program interface and acts to translate commands and other data to a form suitable to be sent to storage controller 104]; [0218 – In Fig. 11, step 1120 comprises caching data corresponding to a backing store 460 on NVM storage media 410]; [0219 – In Fig. 11, step 1130 comprises maintaining access metadata pertaining to data accesses within the logical address space]);
determining a second score for the second data (Talagala, [0220 – In Fig. 11, step 1140 determines whether to admit data of a logical identifier and determining an access metric of the logical identifier]; [0221 - Step 1140 comprises determining whether to admit the data as ‘low-value’ data. If the access metric of a logical identifier does not satisfy the access threshold it may be admitted as ‘low-value’ data]);
comparing the first score (Talagala, [Fig. 16]; [0249 – Fig. 16, step 1630 comprises determining an access metric of the data and a sequentiality metric of the data using access metadata]; [Satisfy admission criteria? Yes]; [0250 - The comparison of step 1640 may be dynamic, according to the values of the access metric and/or the sequentiality metric determined at step 1630]) and the second score (Talagala, [Fig. 11]; [0221 - If the access metric of a logical identifier does not satisfy the access threshold it may be admitted as ‘low-value’ data; Since the claim does not recite how the comparison is done, the citation is a valid interpretation]);
writing the second data to the storage media based on the second score (Talagala, [0222 – In Fig. 11, step 1150 comprises storing the data on a non-volatile storage device]).
The remaining limitations are similar to claims 1-2 and therefore the same mappings are incorporated.
As per Claim 20, it is similar to claims 1,2,4 and therefore the same mappings are incorporated.
Claims 3, 11, 19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698), Yuan (8601223) and Ballapuram et al (20220229778).
As per Claim 3, the rejection of claim 2 is incorporated, and Talagala, Surianarayanan, Yuan disclose cache profiling.
Ballapuram further discloses,
wherein the first data uses a first cache (Ballapuram, [0013 - The device switches the operating mode of a region of the volatile memory from the scratchpad mode to the cache mode, thereby decreasing the size of the scratchpad portion]);
wherein the second data uses a second cache (Ballapuram, [0013 - The device switches the operating mode of a region of the volatile memory from the cache mode to the scratchpad mode, thereby increasing the size of the scratchpad portion]);
wherein the first cache (Ballapuram, [Fig. 5: Operating mode=cache mode? Yes, step 515-Power up associated NVM section, step 520-operation portion in cache mode]; [0101 - At step 515, the section of the NVM associated with the portion is powered up. For example, the device may power up the Way 0 section so that eviction procedures and fill procedures are performed for the portion during operation in the cache mode]) applies a different cache replacement policy than the second cache (Ballapuram, [Fig. 4: Operating mode=scratchpad mode? Yes, step 415-Perform eviction procedures, step 420-Power down associated NVM section, step 430-operate portion in scratchpad mode]; [0090 - At step 415, eviction procedures are performed. For example, the device performs eviction procedures for the Way 0 portion. The eviction procedures are performed as part of the cache mode and before the Way 0 portion is operated in the scratchpad mode at 420]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scratchpad mode of Ballapuram into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of having a device/SSD operate a portion of the volatile memory in a scratchpad mode so that certain requests from the host can be satisfied with deterministic latency. In the scratchpad mode, requests that implicate the portion may be satisfied exclusively by the volatile memory and non-deterministic latency operations used in the cache mode may be avoided, thereby allowing the device to operate according to deterministic latency (Ballapuram, 0013).
As per Claim 11, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 19, it is similar to claim 3 and therefore the same mappings are incorporated.
Claims 6-8, 14-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Talagala (20130185475) in view of Surianarayanan (20220413698), Yuan (8601223) and Haswell (20200183855).
As per Claim 6, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
wherein the one or more entries corresponds to data accessed above a threshold (Yuan, [Col. 5, lines 54-60 - The attributes 620 include one or more contiguous bits 630. If a plurality of contiguous virtual pages 510 are mapped to a plurality of contiguous physical pages 520, the frame address 610 of each corresponding PTE, e.g., PTE 2,3,4,5 may be the physical page number of the base physical page number, lowest address—0020 and the contiguous bits 630 are set to the number of contiguous pages, e.g. 4; It is well known that storing data in contiguous pages is directly related to a high data access rate because it exploits the principle of spatial locality]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
wherein the method further comprises writing data corresponding to the data accessed above a threshold from storage media to the memory media (Haswell, [0039,0040,0041 – In Fig. 3, step 351, performs a host read by performing an L2P Update table lookup at step 352. If the entry is ‘not found’, an L2P Table Cache lookup is performed at step 353. If the entry is not found in the L2P Update portion or the L2P Table Cache, a load region operation is performed at step 354, which loads a L2P region/contiguous/above threshold stored on the NVM/storage media to the memory media]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 7, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
wherein the one or more entries corresponds to data accessed above a threshold (Yuan, [Col. 5, lines 54-60 - The attributes 620 include one or more contiguous bits 630. If a plurality of contiguous virtual pages 510 are mapped to a plurality of contiguous physical pages 520, the frame address 610 of each corresponding PTE, e.g., PTE 2,3,4,5 may be the physical page number of the base physical page number, lowest address—0020 and the contiguous bits 630 are set to the number of contiguous pages, e.g. 4; It is well known that storing data in contiguous pages is directly related to a high data access rate because it exploits the principle of spatial locality]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
wherein the method further comprises storing data corresponding to the data accessed above a threshold in the memory media (Haswell, [0042 – In Fig. 4, at step 460 performing a write operation of the data from the host]; [0043 - At step 462, a determination is made as to whether the L2P Table cache contains the required region/contiguous/above threshold addressing the logical address of the host written data, step 462:No]; [0044 - At step 463, a determination is made as to whether the L2P Update portion contains enough available space to receive an updated TU/translation unit resulting from the host write operation. If yes, then at step 468 the entry is inserted into the L2P Update table, in memory media]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 8, the rejection of claim 5 is incorporated, and Talagala, Surianarayanan, Yuan disclose,
wherein the at least one page table comprises one or more entries (Yuan, [Col. 5, lines 44-48 - Figs. 5-6 show a page table. Each PTE in page table 600 includes a page frame address 610 and one or more attributes 620]);
wherein the one or more entries corresponds to data accessed below a threshold (Yuan, [Col. 5, lines 66-67 - The contiguous bits directly specify the number of contiguous pages. But, a bit value of ‘0’ indicates that the page is not contiguous with another page, thereby implying access below a threshold]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the virtual addressing of Yuan into the cache profiling of Talagala, Surianarayanan for the benefit of utilizing a page table which includes one or more page table entries. Each PTE may also include one or more parameters that are utilized to translate the virtual address to a physical address and access the physical memory device (Yuan, Col. 1, lines 58-64).
Haswell clarifies the storage in the volatile memory media of the SSD/storage device as follows,
wherein the method further comprises modifying data corresponding to the data accessed below a threshold from the memory media to storage media (Haswell, [Fig. 4: steps 461-Host write, step 462-L2P Table cache has required region?Yes, step 466-Update region, step 467-Flush region to NAND]; [0046 – In Fig. 4, after steps 461, 462, at step 466, the L2P Table cache/volatile, is updated with all relevant entries for that region in the L2P Update table in addition to the update required for this host write operation. Once it has been updated/modified the region is written back to the L2P Table stored in NVM/storage media at step 467]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the L2P table of Haswell into the cache profiling of Talagala, Surianarayanan, Yuan for the benefit of using of a part of the volatile memory as a cache for the L2P table, as opposed to requiring sufficient volatile memory to load the entire table at one time, thereby allowing less volatile memory, DRAM or SRAM to be required (Haswell, Para-0013).
As per Claim 14, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 15, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 8 and therefore the same mappings are incorporated.
Response to Arguments
The Applicant's arguments filed on January 02, 2026 have been fully considered, but they are not persuasive.
In attempt to overcome the prior art, the amendments recite improper, inconsistent and/or unsupported subject matter.
Applicant writes: ‘Applicant would like to thank ….During the interview, claim 1 was discussed’. (Rem, Pg. 7)
Response: No agreement was reached.
Applicant argues: ‘Claim 1 is amended…, "receiving a request related to at least one of an operating system and an application," "determining that data corresponding to the request is related to the operating system," and "determining a priority score for the data”’. (Rem, Pg. 8)
Response: The amendments have issues. When claims are amended, they must still be supported by the original disclosure.
Regarding the amendments, nowhere does the spec recite the first limitation. As mentioned in the 112(a), the data is related to (operation of the) OS and/or the (operation of the) application, not the request.
The second limitation is also unsupported by the spec. ‘….data….related to an OS’ is not equivalent to ‘…data….related to an operation of an OS’. Similarly, ‘…data….related to an application’ is not equivalent to ‘data….related to an operation of an application’.
The spec recites, ‘….data related to an operation of an OS’ (not ‘….data related to an OS’).
As explained in the 112(b), ‘….data related to an OS’, focuses mostly on static data, such as all files, configuration data, kernel binary, system binaries, registry keys, system libraries etc., that define the OS.
But ‘….data related to an operation of an OS’ is narrower, and focuses on dynamic, runtime data generated by OS operations like process scheduling, I/O handling, memory management (allocation/deallocation), file system management (creating, moving, deleting files, directories etc.). This is data that changes based on what the system is currently doing, not just what it is.
Therefore reciting, ‘determining….data related to an OS’ is improper and unsupported. Please see the 112(a) and 112(b).
Applicant further argues: ‘The Action argues that an "operation of an operating system" in claim 1 is unclear’. (Rem, Pg. 9)
Response: The term is not defined, or used consistently within the spec, making its interpretation unclear. As mentioned in the previous 112(b), the spec does not recite examples of ‘an operation of an OS’ in relation to the claims. More importantly, the spec does not disclose ‘determining that the data is related to an operation of the OS’. The spec does not disclose the steps/details that determine how the data is related to an operation of the OS. The claim and spec recite a 1-line result, not how the result is achieved. This lack of written description shows lack of possession.
The recitation, ‘….data is….related to the OS’, attempts to circumvent the deficiency of the spec, but it is improper. Please see the 112(a).
Applicant further argues: ‘The Action argues that "it is unclear if the claim 4 recited 'a cache' is associated with 'the first cache' and 'the second cache’. (Rem, Pg. 10)
Response: The limitations fail to clearly define the scope of claims 3-4 and can lead to multiple interpretations.
Applicant further argues: ‘The Action argues that Talagala describes an "operation of an operating system’. (Rem, Pg. 12)
Response: Yes, it does.
The requirement is the claim 1 limitation, ‘determining that data is related to an operation of an operating system’.
The combination of Talagala,Haswell,Yuan disclose the above requirement, wherein Talagala, Para-0167 recites, ‘A storage client may request allocation of a particular logical identifier (e.g. logical address, LBA, physical address, file name etc.). If the index 504 of the storage metadata comprises an entry 505 that includes the requested logical identifier, the logical identifier associated with the request may be identified as being already allocated. If the logical identifier is not in the index, it is allocated to the requester by creating a new entry 505/result in the index 504’. Here the storage client can be an OS (see Para-0140), and allocation is ‘an operation of an OS’. Since the logical identifier/data is used in the allocation operation to create a new entry/result, it implies determining that the logical identifier/data is related to an operation of the OS. Please see O/A.
Examiner Notes:
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
1.’Data storage device employing caching groups defined by write counts of data blocks and operating method thereof’, US20220164292A1, SK Hynix- An operating method of a data storage device includes steps of: checking a write count of each of a plurality of data blocks in a first memory apparatus, setting, as a first bit value, a bit value corresponding to each start position of consecutive data blocks having the same write count as each other, in a bitmap having the same size as the number of the plurality of data blocks, forming a plurality of caching groups each including one or more data blocks by using the first bit value and caching data stored in the first memory apparatus to a second memory apparatus on a caching group basis.
2.’Non-volatile storage addressing using multiple tables’, US20130198439A1, Hitachi - The control unit is characterized by storing in the first memory the first table,LPT for translating a logical address of data of the first memory to a physical address, storing in the second memory a cache of the first table,LPT-C and a second table, an area table, for showing where in the first memory the first table is stored, and further storing in the second table multiple addresses, of the first table in the first memory.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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