DETAILED ACTION
Reissue
The present reissue application is directed to US 11,482,514 B2 (“514 Patent”). 514 Patent issued on October 25, 2022 with claims 1-20 from application 16/803,485 filed on February 27, 2020, and claims priority to JP 2019-166972 filed on September 13, 2019.
This application was filed on October 24, 2024. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the first inventor to file provisions of the AIA .
This application presents broadened claims, which are permitted because Applicant filed these claims and demonstrated an intent to broaden within two years of the issue date of 514 Patent.
The most recent amendment was filed on October 24, 2024. The status of the claims is:
Claims 1-20: Original
Claims 21-25: New
This is a first, non-final action.
References and Documents Cited in this Action
514 Patent (US 11,482,514 B2)
Mushiga (US 10,354,987 A)
Matsuo (US 2018/0277497 A1)
Fukuzumi (US 2018/0374864 A1)
Summary of Rejections and Objections in this Action
Examiner objects to the drawings.
Claims 21-25 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
Claims 21-25 are rejected under 35 U.S.C. 251 as being based upon new matter added to the patent for which reissue is sought
Claims 21-25 are also rejected under 35 U.S.C. 251 for not being the same invention as that disclosed as being the invention in the original patent.
Summary of the Claims
514 Patent is generally directed to a semiconductor storage device including a plurality of first pads on an edge region of a first chip and a plurality of second pads on an edge region of a second chip. Claim 1 is representative:
1. A semiconductor storage device comprising:
a first chip including
a plurality of memory cells provided on a first substrate in a memory cell region,
a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, wherein the edge region of the first chip includes first, second, third, and fourth sides that surround the memory cell region and at least four of the first pads are arranged along a first direction on the first side of the edge region of the first chip, and wherein inside the first chip:
a first one of the first pads is not electrically connected to a second one of the first pads and a third one of the first pads is not electrically connected to a fourth one of the first pads; and
the second one of the first pads is electrically connected to the third one of the first pads, and
a first conductive layer provided on the first substrate and electrically connected to the first pads; and
a second chip including
a first circuit provided on a second substrate in a circuit region,
a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, wherein the edge region of the second chip includes first, second, third, and fourth sides that surround the circuit region and at least four of the second pads are arranged along the first direction on the first side of the edge region of the second chip, and wherein inside the second chip:
a first one of the second pads is electrically connected to a second one of the second pads and a third one of the second pads is electrically connected to a fourth one of the second pads; and
the second one of the second pads is not electrically connected to the third one of the second pads, and
a second conductive layer provided on the second substrate and electrically connected to the second pads,
wherein the first, second, third, and fourth ones of the first pads of the first chip and the first, second, third, and fourth ones of the second pads of the second chip are respectively bonded facing each other.
Claims 1, 11, and 21 are the independent claims. Claim 21 further recites, among other things, insulating films. Claim 11 recites a method that corresponds to the apparatus of claim 1.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the insulating films must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.173(b)(3) are required in reply to the Office action to avoid abandonment of the application. Applicant must submit a replacement sheet for each sheet of drawings containing a Figure to be revised. Any replacement sheet must comply with 37 CFR 1.84 and include all of the figures appearing on the original version of the sheet, even if only one figure is being amended. Each figure that is amended must be identified by placing the word “Amended” at the bottom of that figure. Any added figure must be identified as “New.” In the event that a figure is canceled, the figure must be identified as “Canceled” and also surrounded by brackets. All changes to the figure(s) must be explained, in detail, beginning on a separate sheet which accompanies the papers including the amendment to the drawings. See MPEP 1413 for further information.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claim 21, 514 Patent does not particularly disclose “a first insulating film covering the memory cells and having a first bonding face extending in the first direction and the second direction” or “a second insulating film covering the first circuit and having a second bonding face extending in the first direction and the second direction” as recited in the claim. 514 Patent also does not particularly disclose “a plurality of first pads provided in the first insulating film”; “a first conductive line provided in the first insulating film; “a plurality of second pads provided in the second insulating film”; “a second conductive line provided in the second insulating film”; and “a third conductive line provided in the second insulating film” as recited in the claim.
Examiner acknowledges that 514 Patent discloses a first chip including a plurality of first pads 318 and a first conductive line 316; and a second chip including a plurality of second pads 313 and second and third conductive lines 311 (i.e., Figure 13). 514 Patent also generally discloses insulating films between conductive layers (e.g., “Among these conductive layers, conductive layers adjacent to each other in the Z direction are stacked via the interlayer insulating films”; column 10, lines 27-29; “In FIG. 6 to FIG. 11, interlayer insulating films between conductive layers are omitted”; column 11, lines 47-48).
However, 514 Patent does not describe additional details regarding the insulating films or the relationship of the insulating films to other elements. For example, 514 Patent does not describe “covering” memory cells and circuits with insulating films. 514 Patent does not describe a relationship between insulating films and disclosed bonding surfaces (e.g., the bonding surfaces of chips 300 and 200 shown in Figure 13 are not disclosed as bonding surfaces of insulating films). Furthermore, 514 Patent does not describe pads 318 and 313 and conductive lines 316 and 311 in relation to an insulating film.
Therefore, “a first insulating film covering the memory cells and having a first bonding face extending in the first direction and the second direction”; “a plurality of first pads provided in the first insulating film”; “a first conductive line provided in the first insulating film; “a second insulating film covering the first circuit and having a second bonding face extending in the first direction and the second direction”; “a plurality of second pads provided in the second insulating film”; “a second conductive line provided in the second insulating film”; and “a third conductive line provided in the second insulating film” are not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventors, at the time the application was filed, had possession of the claimed invention.
Claims 22-25 depend on claim 21 and are rejected for at least the same reason. 514 Patent also does not disclose “the second and third conductive lines are physically separated by the second insulating film” as recited in claim 25 because again, 514 Patent does not describe conductive lines 311 in relation to an insulating film.
Claim Rejections - 35 USC § 251
Claims 21-25 are rejected under 35 U.S.C. 251 as being based upon new matter added to the patent for which reissue is sought. The added material which is not supported by the prior patent is as follows:
“a first insulating film covering the memory cells and having a first bonding face extending in the first direction and the second direction”; “a plurality of first pads provided in the first insulating film”; “a first conductive line provided in the first insulating film; “a second insulating film covering the first circuit and having a second bonding face extending in the first direction and the second direction”; “a plurality of second pads provided in the second insulating film”; “a second conductive line provided in the second insulating film”; and “a third conductive line provided in the second insulating film” (e.g., claim 21); and
the second and third conductive lines are physically separated by the second insulating film” (e.g., claim 25).
See the related discussion above with respect to 35 U.S.C. 112(a).
Claims 21-25 are also rejected under 35 U.S.C. 251 for not being the same invention as that disclosed as being the invention in the original patent. See MPEP 1412.01; United States Industrial Chemicals, Inc. v. Carbide & Carbon Chemicals Corp., 315 U.S. 668, 53 USPQ6 (1942); Antares Pharma Inc., v. Medac Pharma Inc. and Medac GMBH, 771 F.3d1354, 112 USPQ2d 1865 (Fed. Cir. 2014); and Forum US, Inc. v. Flow Valve, LLC, 926 F.3d 1346, 1352, 2019 USPQ2d 221227 (Fed. Cir. 2019).
Claims 21-25 are directed to an invention including a first chip having “a first insulating film covering the memory cells and having a first bonding face extending in the first direction and the second direction,” “a plurality of first pads provided in the first insulating film,” and “a first conductive line provided in the first insulating film; and a second chip having “a second insulating film covering the first circuit and having a second bonding face extending in the first direction and the second direction,” “a plurality of second pads provided in the second insulating film,” “a second conductive line provided in the second insulating film,” and “a third conductive line provided in the second insulating film.” This invention is not clearly and unequivocally disclosed in the specification as a separate invention with the claimed combination of features.
514 Patent is directed to a semiconductor storage device including a first chip having a first conductive line and a plurality of first pads; and a second chip having second and third conductive lines and a plurality of second pads (e.g., Figure 13). However, 514 Patent does not disclose these elements in relation to insulating films; e.g., 514 Patent does not describe conductive lines or pads “provided in” an insulating film. 514 Patent also does not describe insulating films “covering” memory cells and circuits or having bonding faces.
Even if one of ordinary skill in the art would understand that the elements in question would be possible (e.g., a first or second chip with an insulating film having a bonding face; or conductive lines and a plurality of pads provided in an insulating film, in combination with the other elements recited in claim 21), the claims are insufficient to comply with the standard for original patent set forth by the Federal Circuit. Therefore, claims 21-25 are drawn to an invention comprising a newly claimed combination of features that are not disclosed as an invention separate from the original invention and do not satisfy the original patent requirement of 35 U.S.C. 251.
Allowable Subject Matter
Claims 1-20 are allowed.
Mushiga teaches, among other things, a first chip 1000 having a plurality of first pads 318 and a second chip 4000 having a plurality of second pads 498, wherein first pads of the first chip and the second pads of the second chip are respectively bonded facing each other (Figure 18A).
Matsuo teaches, among other things, a first chip 150 having plurality of first electrodes 102 and a second chip 350 having a plurality of second electrodes 301, wherein first electrodes of the first chip and the second electrodes of the second chip are respectively bonded facing each other (Figure 9).
Fukuzimi teaches, among other things, a first chip 100 having plurality of first pads 73 and a second chip 200 having a plurality of second interconnection layers 76, wherein first interconnection layers of the first chip and the second interconnection layers of the second chip are respectively bonded facing each other (Figure 1).
The prior art does not specifically disclose or fairly teach a semiconductor storage device or a method of forming a semiconductor storage device including the combination of all of the elements, steps, and limitations recited in claims 1-20, particularly wherein:
a first one of the first pads is not electrically connected to a second one of the first pads and a third one of the first pads is not electrically connected to a fourth one of the first pads; and
the second one of the first pads is electrically connected to the third one of the first pads, and
a first one of the second pads is electrically connected to a second one of the second pads and a third one of the second pads is electrically connected to a fourth one of the second pads; and
the second one of the second pads is not electrically connected to the third one of the second pads.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992