DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-4 and 20 are objected to because of the following informalities:
Claim 1 recites the limitation "each of the power stage circuit" [sic] in line 3.
Claims 2-7 inherit the same from claim 1.
Claim 8 recites the limitation "each of the power stage circuit" [sic] in line 4.
Claims 9-14 inherit the same from claim 8.
Claim 20 recites the limitation "a plurality of report signal" [sic] in line 3.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 8, 14, 15 and 19 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Qiu et al. (US 20080197824).
Claim 1; Qiu et al. disclose a control circuit for a multiphase voltage regulator, comprising: a switching control circuit (e.g. fig. 5) configured to provide a plurality of control signals to control a plurality of power stage circuits (440-1 to 440-4), wherein each power stage circuit is configured to provide a phase current (e.g. fig. 6a); and a monitor circuit (420) configured to receive at least one report signal from at least one of the power stage circuits, and determine whether the report signal indicates an activated phase (see fig. 7); wherein after the report signal indicating the activated phase is received, the control signal is provided to the power stage circuit determined as the activated phase [para. 0042].
Claim 7; Qiu et al. disclose the monitor circuit is configured to obtain a phase number of the power stage circuits according to the report signal indicating the activated phase (see fig. 7; the phase numbers are known and reported).
Claim 8; Qiu et al. disclose a control circuit (e.g. fig. 5) for a multiphase voltage regulator, comprising: a switching control circuit configured to provide a plurality of control signals; a plurality of switching control pins (from 410), each of which is configured to be coupled to a plurality of power stage circuits, wherein each power stage circuit is configured to provide a phase current; and a monitor circuit (420/462/510) configured to receive a plurality of voltage signals (e.g. from 410/461/515) of the switching control pins, determine whether the voltage signal of the switching control pin indicates an activated phase (fig. 7), and obtain a phase number (fig. 7) of the power stage circuits according to the voltage signals of the switching control pins.
Claim 14; Qiu et al. disclose the monitor circuit is configured to obtain a phase number of the power stage circuits according to the voltage signal of the switching control pin (shown in fig. 7).
Claim 15; Qiu et al. disclose a multiphase voltage regulator, comprising: a plurality of power stage circuits (440-1 – 440-4), each of which is configured to provide a phase current, wherein each power stage circuit comprise at least one power switch and a report pin (I-1 – I_N), wherein the report pin is configured to provide a report signal (currents I-1 – I_N); and a control circuit (420/462/510) coupled to the power stage circuits, wherein the control circuit is configured to: receive at least one report signal from at least one of the power stage circuits, determine whether the report signal indicates an activated phase; and provide a control signal to the corresponding power stage circuit determined as the activated phase (fig. 7).
Claim 19; Qiu et al. disclose the control circuit is configured to obtain a phase number of the power stage circuits according to the report signal indicating the activated phase (shown in fig. 7).
Allowable Subject Matter
Claims 2-6, 9-13 and 16-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten or amended to overcome the objection(s) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2-6; prior art fails to disclose or fairly suggest, inter alia, provide the control signal with a high impedance mode to all of the switching control pins during an initial period; wherein a plurality of the report signals are received via the switching control pins; wherein the monitor circuit is further configured to compare each of the report signal with a middle voltage level; and wherein the monitor circuit is configured to determine that the corresponding power stage circuit is the activated phase when the report signal matches the middle voltage level.
Claims 9-13; prior art fails to disclose or fairly suggest, inter alia, the monitor circuit is further configured to compare each of the voltage signal of the switching control pin with a middle voltage level, and determine that the corresponding power stage circuit is the activated phase when the voltage signal of the switching control pin matches the middle voltage level.
Claims 16-18; prior art fails to disclose or fairly suggest, inter alia, to provide the control signal with a high impedance mode to all of the switching control pins during an initial period; wherein a plurality of the report signals are received via the switching control pins; wherein the control circuit is further configured to compare each of the report signal with a middle voltage level; and wherein the control circuit is configured to determine that the corresponding power stage circuit is the activated phase when the report signal matches the middle voltage level.
Claim 20; prior art fails to disclose or fairly suggest, inter alia, a method comprises: determining whether a first report signal received from a first power stage circuit is greater than a voltage threshold, wherein when the first report signal is greater than the voltage threshold, the first power stage circuit is determined as ready; after the first report signal is greater than the voltage threshold, determine whether each of the report signals is greater than the voltage threshold, wherein the corresponding power stage circuit is determined as an activated phase when the report signal is greater than the voltage threshold; and providing at least one control signal to the corresponding power stage circuit determined as the activated phase.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20070234078 Nguyen disclose a multiphase voltage regulator; US 20050073288 Harris discloses a current mode regulator; US 2004014845 Schuellen discloses a multiphase buck converter; US 20030090255 Bassett disclose bus control for a multiphase converter; US 20020118001 Duffy et al. disclose a phased power regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 7/22/2026
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