DETAILED ACTION
The present application, filed 10/24/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 3-7, 17, and 19 are objected to because of the following informalities:
Re claim 3, it appears that “the current sense pins” (line 5) should be “the plurality of current sense pins”.
Re claim 4, it appears that “the voltage” (line 2) should be “a voltage”.
Re claim 5, it appears that “the voltage” (line 2) should be “a voltage”.
Re claim 6, it appears that “the first switches” (line 5) should be “the plurality of first switches”.
Re claim 7, it appears that “the initial period” (line 4) should be “an initial period”. It appears that “the second switches” (line 4) should be “the plurality of second switches”. It appears that “the first switches” (line 5) should be “the plurality of first switches”. It appears that “the current sense” (line 5) should be “a current sense”.
Re claim 17, it appears that “the power stage circuits” (line 8) should be “the plurality of power stage circuits”. It appears that “the pre-charge” (line 9) should be “a pre-charge”.
Re claim 19, it appears that “the power stage” should be “the plurality of power stage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 12 recites the limitation "the switch". There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the switch". There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the switch". There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the switch". There is insufficient antecedent basis for this limitation in the claim.
Re claim 20, it is unclear what “the reporting signal” is referring to. Is it referring to one of the plurality of reporting signals, or something else?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang et al. (“Jiang”, US 7,224,218).
Re claim 10, Jiang teaches a power stage circuit [Fig 1], comprising: a switch circuit having at least one switch [P1], wherein one of the at least one switch is configured to be coupled to a flying capacitor [C2]; a driving control circuit [12] configured to receive a control signal [at en] and provide at least one driving signal [output of 12] to a control terminal of the at least one switch; a pre-charge monitor circuit [K1] configured to monitor a voltage across the flying capacitor; and a report circuit [18] configured to provide a report signal [input to + terminal of K1] indicating a pre-charge period of the flying capacitor is finished [Col 4, ln 66 – Col 5, ln 5].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 17, 18, and 20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Lazaro et al. (“Lazaro”, US 2025/0246987).
Re claim 1, Jiang teaches a control circuit for a multiphase voltage regulator, comprising: a switching control circuit [20] configured to provide a control signal [output of 20], wherein each of the power stage circuit is configured to provide a phase current; and a monitor circuit [14] configured to receive a report signal [input to + terminal of K1] from at least one of the power stage circuits, and determine whether the report signal indicates a pre-charge period of the corresponding power stage circuit is finished [Col 4, ln 66 – Col 5, ln 5]; wherein after the report signal indicates that the pre-charge period of the corresponding power stage circuit is finished, the control signal is provided to power on the corresponding power stage circuit [Col 4, ln 66 – Col 5, ln 5] but does not teach a plurality of power stage circuits.
Lazaro teaches a device [Fig 2] having a plurality of control circuits [204A-D]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jiang to include the features of Lazaro because it is used to distribute load current across multiple parallel phases, which reduces RMS, thus improving the utility of the device, which increases efficiency.
Re claim 2, Jiang teaches wherein the monitor circuit is configured to compare the report signal with a voltage threshold [input to – terminal of K1] and generate a comparison signal [output of K1] in response to the report signal and the voltage threshold; and determine whether the pre-charge period of the corresponding power stage circuit is finished according to the comparison signal [Col 4, ln 66 – Col 5, ln 5].
Re claim 17, Jiang teaches a voltage regulator, comprising: a power stage circuit comprising at least one power switch [P1] and a report circuit [18], wherein the report circuit is configured to provide a report signal [input to + terminal of K1]; and a control circuit [14] coupled to the power stage circuits; wherein the control circuit is configured to receive the report signal from at least one of the power stage circuits, determine whether the report signal indicates the pre-charge period of the corresponding power stage circuit is finished [Col 4, ln 66 – Col 5, ln 5]; and provide a control signal to the corresponding power stage circuit after it is determined that the report signal indicates the pre-charge period of the corresponding power stage circuit is finished [Col 4, ln 66 – Col 5, ln 5] but does not teach a plurality of power stage circuits, each of which is configured to provide a phase current.
Lazaro teaches a device [Fig 2] having a plurality of control circuits [204A-D], each of which is configured to provide a phase current [paragraph 25]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jiang to include the features of Lazaro because it is used to distribute load current across multiple parallel phases, which reduces RMS, thus improving the utility of the device, which increases efficiency.
Re claim 18, Jiang teaches wherein the control circuit is further configured to compare the report signal with a voltage threshold [input to – terminal of K1] and generate a comparison signal [output of K1] in response to the report signal and the voltage threshold; and determine whether the pre-charge period of the corresponding power stage circuit is finished according to the comparison signal [Col 4, ln 66 – Col 5, ln 5].
Re claim 19, Jiang teaches wherein the control circuit is further configured to determine whether all of the report signal indicates the pre-charge period of all of the corresponding power stage circuits are finished [Col 4, ln 66 – Col 5, ln 5]; and provide a plurality of the control signals to the power stage circuits after it is determined that the report signals indicate that the pre-charge period of all of the corresponding power stage circuits are finished [Col 4, ln 66 – Col 5, ln 5], but does not teach a plurality of power stage circuits.
Lazaro teaches a device [Fig 2] having a plurality of control circuits [204A-D]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jiang to include the features of Lazaro because it is used to distribute load current across multiple parallel phases, which reduces RMS, thus improving the utility of the device, which increases efficiency.
Re claim 20, Jiang teaches a method for controlling a voltage regulator, comprises: receiving reporting signal [input to + terminal of K1] from a power stage circuit; determining whether the reporting signal indicates a pre-charge period of the corresponding power stage circuit is finished [Col 4, ln 66 – Col 5, ln 5]; after the reporting signal indicating the pre-charge period of the corresponding power stage circuit is finished, providing a control signal [output of 20] to power on the corresponding power stage circuit [Col 4, ln 66 – Col 5, ln 5], but does not teach a plurality of power stage circuits.
Lazaro teaches a device [Fig 2] having a plurality of control circuits [204A-D]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Jiang to include the features of Lazaro because it is used to distribute load current across multiple parallel phases, which reduces RMS, thus improving the utility of the device, which increases efficiency.
Allowable Subject Matter
Claims 3-9, 11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose:
Re claim 3 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a plurality of the report signals are received via the current sense pins; and a plurality of voltage reference circuits coupled to the current sense pins, wherein each of the voltage reference circuit is configured to connect the corresponding current sense pin to a voltage reference” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 8 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the monitor circuit is configured to determine that the pre-charge period of the corresponding power stage circuit is finished when a falling edge of the report signal is detected” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 9 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the monitor circuit is configured to determine that the pre-charge period of the corresponding power stage circuit is finished when a rising edge of the report signal is detected” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 11 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the report circuit includes a switch coupled to a reference voltage, the switch is turned on when the voltage across the flying capacitor is not greater than a threshold, and the switch is turned off after the voltage across the flying capacitor is greater than the threshold” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 12 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a current sense pin configured to provide a current sense signal to a control circuit for a multiphase voltage regulator, wherein the report signal is provided via the current sense pin; wherein the switch is coupled between the reference voltage and the current sense pin” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 13 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “after the switch is turned off, the report signal is less than a voltage threshold indicates that the pre-charge period of the corresponding power stage circuit is finished” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 14 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “after the switch is turned off, a falling edge of the report signal indicates that the pre-charge period of the corresponding power stage circuit is finished” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 15 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “after the switch is turned off, a rising edge of the report signal is detected indicates that the pre-charge period of the corresponding power stage circuit is finished” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 16 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the switch circuit further comprising: a first high-side switch having a first terminal, a second terminal and a third terminal, wherein the first terminal of the first high-side switch is configured to receive an input voltage; a first low-side switch having a first terminal, a second terminal and a third terminal, wherein the first terminal of the first low-side switch is coupled to the second terminal of the first high-side switch via the flying capacitor, and the second terminal of the first low-side switch is configured to be coupled to a reference voltage level” in combination with the additionally claimed features, as are claimed by Applicant.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Examiner, Art Unit 2838
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