DETAILED ACTION
The current Office Action is in response to the papers submitted 06/05/2026. Claims 1-6 and 8 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 - 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “providing, for at least a second time period, the fallback clock signal or no signal as the clock output signal” in lines 7 – 8. It is unclear how a clock output signal can be no signal. If there is no signal then there is no clock output signal. Saying the clock output signal is provided for a time period would appear to exclude a situation where there is no clock output signal since the clock output signal is a signal that is provided somewhere.
Claim 5 recites the limitation “providing the fallback clock signal or no signal as the clock output signal” in lines 5 - 6. It is unclear how a clock output signal can be no signal. If there is no signal then there is no clock output signal. Saying the clock output signal is provided for a time period would appear to exclude a situation where there is no clock output signal since the clock output signal is a signal that is provided somewhere.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 6, 8 - 11, 13 – 16, and 18 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Felix et al. (Pub. No.: US 2021/0191488) referred to as Felix.
Regarding claim 1, Felix teaches a method of evaluating the performance of a droop mitigation scheme [Fig 8; Paragraphs 0036 – 0049; The process performed is a droop mitigation scheme], wherein the method is carried out at a circuit [Fig 1; Paragraph 0027; Figure 1 is a circuit], the method [Fig 8; Paragraphs 0036 – 0049] comprising:
receiving a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal [Paragraphs 0036 – 0049; The scheme uses the clock 4 to generate a clock output signal that is received at mitigation circuitry 11]; and
analyzing the clock output signal to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme [Fout, Fig 2; Paragraphs 0040 – 0046 and 0051; The magnitude of the droop provides an indication of the performance of the droop mitigation scheme. It checks how effective the previous adjustment of the clock frequency has mitigated the voltage drop. The droop mitigation measurements are adjusted periodically based on the magnitude].
Regarding claim 2, Felix teaches using the droop mitigation scheme to generate the clock output signal,
wherein the droop mitigation scheme comprises adjusting the frequency of the clock output signal in response to a droop event [Figs 1 – 2, 4, and 8; Paragraphs 0036 – 0049; The mitigation scheme creates the clock using 4 and the scheme includes changing the frequency or pausing the clock by removing pulses or adding pulses].
Regarding claim 3, Felix teaches using the droop mitigation scheme to generate the clock output signal comprises:
receiving a plurality of clock input signals, the plurality of clock input signals comprising a nominal clock signal and a fallback clock signal;
providing, for at least a first time period, the nominal clock signal as the clock output signal; and
providing, for at least a second time period, the fallback clock signal or no signal as the clock output signal [Figs 1 – 2; Paragraphs 0031 and 0036; The clock source provides either an output of a first PPL or an output of a second PPL which have different speed. The clockgating function blocks a clock signal resulting in no clock signal].
Regarding claim 4, Felix teaches monitoring a supply voltage for a voltage droop event [Paragraph 0050; The droop detector measures a voltage].
Regarding claim 5, Felix teaches using the droop mitigation scheme to generate the clock output signal [Paragraphs 0036 – 0049; The scheme uses the clock 4 to generate a clock output signal that is received at mitigation circuitry 11] further comprises:
initially providing the nominal clock signal as the clock output signal;
responsive to detecting a voltage droop event, providing the fallback clock signal or no signal as the clock output signal [Figs 1 – 2; Paragraphs 0031 – 0032; When a voltage droop is detected the mitigation circuit 11 changes a current clock to another clock where the frequency between the clocks are different].
Regarding claim 6, Felix teaches the nominal clock signal and the fallback clock signal have different frequencies [Figs 1 – 2; Paragraphs 0031 – 0032; When a voltage droop is detected the mitigation circuit 11 changes a current clock to another clock where the frequency between the clocks are different].
Regarding claim 8, Felix teaches evaluating the performance of the droop mitigation scheme [Fout, Fig 2Paragraphs 0040 – 0046 and 0051; The magnitude of the droop provides an indication of the performance of the droop mitigation scheme. It checks how effective the previous adjustment of the clock frequency has mitigated the voltage drop. The droop mitigation measurements are adjusted periodically based on the magnitude] comprises:
comparing an output value of the output with one or more thresholds [Paragraphs 0037 - 0038 and 0047 - 0048; The output is compared to a threshold to know if clock pulses need to be removed or not].
Regarding claim 9, Felix teaches evaluating the performance of the droop mitigation scheme [Fout, Fig 2Paragraphs 0040 – 0046 and 0051; The magnitude of the droop provides an indication of the performance of the droop mitigation scheme. It checks how effective the previous adjustment of the clock frequency has mitigated the voltage drop. The droop mitigation measurements are adjusted periodically based on the magnitude] comprises:
in response to determining that the output is below a threshold, providing a droop performance indication signal or adjusting the droop mitigation scheme [Figs 1 – 2; Paragraphs 0038 – 0046; The output is compared to a threshold and as a result an indication of the droop magnitude is provided which is a performance indication signal which is used to adjust the droop mitigation scheme by adjusting the clock].
Regarding claim 10, Felix teaches the circuit comprises a clock circuit comprising a plurality of clock sources and a clock mux, wherein the plurality of clock sources comprises a nominal clock source and a fallback clock source [4, Figs 1 – 2; Paragraphs 0031 - 0032 and 0038 – 0046; Clock source 4 provides two clock signals as the output. This shows the clock source 4 contains a first PLL to provide a first clock, a second PLL to provide a second clock, and a mux or functionally similar device that selects as an output one of two different clock signals with different frequencies from each other].
Regarding claim 11, Felix teaches the circuit comprises a droop detector configured to detect droop in the nominal clock signal [Figs 1 – 2; Paragraphs 0031 – 0032; The circuit detects a droop in both clock signals].
Regarding claim 13, Felix teaches the circuit [Figs 1 – 2] comprises a delay monitor [11 and 13, Figs 1 – 2 and 5] configured to generate the output [Fout, Fig 2], the delay monitor [11 and 13, Figs 1 – 2 and 5] comprising at least one delay line [52, Fig 5] and an encoder [54, Fig 5].
Claims 14 - 16 are a circuit corresponding to claim 1 and is rejected using the same prior art and reasoning as applied to claim 1.
Claim 18 is a system corresponding to claim 1 and is rejected using the same prior art and reasoning as applied to claim 1. Felix teaches the system is circuitry [Fig 2; Figure 2 shows a system comprised of circuitry to monitor droop mitigation] comprising a delay monitor [13, Fig 5; Paragraph 0051; A delay in signal propagation is monitored in 13] and implemented as a chip that is all packaged on a board [Fig 1; Paragraph 0027; Figure 1 is a circuit which may be a system on a chip on a card. The card or cards are in a rack]
Claim 19 is a corresponding product of claim 1 and is rejected using the same prior art and reasoning as applied to claim 1. Felix teaches the product [Fig 1].
Claim 20 is a medium storing code for performing a method corresponding to claim 1 and is rejected using the same prior art and reasoning as applied to claim 1. Felix teaches the medium storing code for performing a method [Fig 8; The functions disclosed in figure 8 indicate code that is stored in memory that dictate how the system operates according to the method of claim 8].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Felix et al. (Pub. No.: US 2021/0191488) referred to as Felix as applied to claims 11 and 16 above, and further in view of Aman Vats (State Machines: Unleashing the Power of Backend-Driven Systems) referred to as Vats.
Regarding claim 12, Felix teaches droop mitigation scheme configured to provide a clock selection signal to the clock circuit in response to detection of droop in the nominal clock signal by the droop detector [4, Figs 1 – 2; Paragraphs 0031 – 0032 and 0036 – 0049; When a voltage droop is detected the mitigation circuit 11 selects a different clock signal where the frequency between different clock signals are different].
However, Felix may not specifically disclose the limitation(s) of a state machine.
Vats discloses the use of state machines to switch operation in a system [Pages 1 – 7].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Vats in Felix, because the use of state machines provides for an efficient approach to modeling a system, allows for simplifying design and implementation of processes, and ensures the system responds predictably and appropriately to different inputs and conditions [Benefits of State Machines, Pages 5 – 6; Conclusion, Pages 6 – 7] .
Claim 17 is a circuit corresponding to claim 12 and is rejected using the same prior art and similar reasoning.
Response to Arguments
Applicant's arguments filed 06/05/2026 have been fully considered but they are not persuasive.
The applicant argues on page 8 that claims 3 and 5 are clear since the phrase “as the clock output signal” implies a clock output signal supplies no which means the clock output signal lacks any signal. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The claims positively state that the clock output signal is provided at a second time period. Providing a clock output signal means some signal is provided. A signal is either a constant steady signal or is a signal that changes value over time. Providing a signal that is no signal is indefinite. Providing no signal means no output signal is provided. A clock output signal cannot be no signal. If there is no signal then there is no clock output signal provided. The claims require some type of signal to be provided as the clock output signal. It appears what the applicant is arguing is that at the second time period either the fallback clock signal is provided at the clock output signal or no clock output signal is provided. However, this is not what the claim currently states. The claims currently state providing no signal as a signal which is unclear and indefinite. It is unknown in the art how a signal can be no signal.
The applicant argues on pages 9 – 10, regarding claim 1, that Felix fails to teach generating a clock output using a droop mitigation scheme or analyzing a clock output signal to generate an output which provides an indication of the performance of the droop mitigation scheme. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no definitive definition in the claim that defines what is and is not a droop mitigation scheme. Everything that happens in figure 2 and 8 is part of an overall droop mitigation scheme. The processes that are performed in items 13, 20, and 21 in figure 2 cannot occur without the clock generated from clock 4. This shows everything from the clock signal Fin generated from clock 4 to the generation of the final clock signal Fout is part a droop mitigation scheme.
The output of 13 is an indication of the performance of the droop mitigation scheme. There is no mention in the claims as to what is meant as an indication of the performance of the droop mitigation scheme. The magnitude of the droop is an indication of the performance of the steps that measure the droop to provide the droop to 20. This indicates the droop mitigation scheme performed a step which is a performance of the droop mitigation scheme.
The applicant argues on page 11 that claims 2 – 6 and 8 – 20 are allowed for containing limitations argued allowed in claim 1 above or for being dependent on a claim containing the limitations argued allowable in claim 1 above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding claim 1 showing how the prior art teaches the argued limitations. The rejections of claims 2 – 6 and 8 – 20 are maintained based in part on the rejection of claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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