DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112 - Indefinite
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 6 recites “substantially equal thresholds”. It is not clear how “equal” the thresholds must be to be “substantially equal”. In other words, it is not clear how different the thresholds can be (e.g., 5%, 10%, or some other value) and still be “substantially equal”. The Examiner also notes that the application does not appear to use the term “substantially” outside of the claims, so there does not appear to be any guidance as to how to interpret this term.
Claims 2-6 are rejected because they depend from claim 1 and fail to further limit the scope in a manner to overcome the rejection.
Claim 7, line 6 recites “substantially equal thresholds”. It is not clear how “equal” the thresholds must be to be “substantially equal”. In other words, it is not clear how different the thresholds can be (e.g., 5%, 10%, or some other value) and still be “substantially equal”. The Examiner also notes that the application does not appear to use the term “substantially” outside of the claims, so there does not appear to be any guidance as to how to interpret this term.
Claims 8-11 are rejected because they depend from claim 1 and fail to further limit the scope in a manner to overcome the rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,736,312 (Tousignant) at FIG. 2 illustrates an offset compensation circuit with first, second, and third differential amplifiers 111, 230A, 230B.
PNG
media_image1.png
462
692
media_image1.png
Greyscale
See also the paragraph spanning cols. 5-6:
(22) FIG. 2 is a block diagram of an illustrative signal comparison system 200 having an input offset compensation circuit 220. As described above with reference to FIG. 1, a source signal 112 may be compared to the reference signal 117 using the comparison circuit 110 to provide a synchronizing signal 119. In some cases, a differential AC source signal may be provided to both inputs 112 and 117 of the comparison circuit 110. In any case, the resulting synchronizing signal 119 may be provided to a compensation circuit 220 to compensate for the input offset voltage of the comparator 111 of the comparison circuit 110. The compensation circuit 220 may include a compensation comparator 130 having two or more comparators 230A, 230B. The compensation circuit 220 may also include two or more voltage accumulators 240A, 240B. Optionally, the compensation circuit 220 may include one or more filters 250A, 250B coupled to the voltage accumulators 140A, 140B.
This does not appear to teach the particular arrangement for at least the second and third differential amps and their base input terminals biased to equal thresholds of opposite polarity to offset zero-crossing points if the second and third differential pair amps relative to a nominally zero-crossing point of the first differential pair amplifier. However, as discussed above, it is not clear how to interpret “substantially” in the claims. After the scope of “substantially” is more clearly defined, a follow-up search will be required.
US 5,182,476 (Hanna) at FIG. 1 illustrates an offset cancellation circuit 10 including first, second, and third differential amps 16, 18, 28.
PNG
media_image2.png
496
794
media_image2.png
Greyscale
See also col 2:
(2) An offset cancellation circuit 10 is shown in FIG. 1 for reducing pulse pairing as the differential analog input signal, V.sub.IN, from the read/write heads of a computer disk drive (not shown) is converted to a clock signal CLOCK corresponding to the peak of the analog input signal. The analog input signal V.sub.IN is differentiated through differentiator 12 for providing differential currents I.sub.12 and I.sub.12 ' flowing into summing junction 14. The differential output signal of summing junction 14 is amplified by gain stage 16 and applied to the non-inverting and inverting inputs of comparator 18.
This does not appear to teach the particular arrangement for at least the second and third differential amps and their base input terminals biased to equal thresholds of opposite polarity to offset zero-crossing points if the second and third differential pair amps relative to a nominally zero-crossing point of the first differential pair amplifier. However, as discussed above, it is not clear how to interpret “substantially” in the claims.
US 4,345,169 (Saleh) at FIG. 2 illustrates a zero crossing detector including first, second, and third differential amps 20, 28, 30.
PNG
media_image3.png
274
382
media_image3.png
Greyscale
See also cols. 2-3:
(4) FIG. 2 shows a preferred embodiment of the present invention. This circuit includes a voltage comparator 20 having two inputs 22 and 24 and an output 26. The inputs 22 and 24 are connected to receive signals from a non-inverting amplifier 28 and an inverting amplifier 30, respectively. Both the non-inverting amplifier and inverting amplifier receive a common input signal applied to the input terminal 32 of the circuit. Voltage bias for the circuit is provided by a resistor network supplied from a terminal 34 receiving a DC voltage.
(5) The two amplifiers 28 and 30 preferably have identical gain. In practice, these amplifiers may be provided in the same integrated circuit, such as an LM358. The voltage comparator may be provided on the same or another integrated circuit, such as one-half of an LM392.
(6) The outputs of the amplifiers 28 and 30 may be connected directly to the respective inputs of the amplifier 20, or may be connected thereto through a double-throw, double-pole switch 36. The switch is operative to interchange the connections of the amplifiers 28 and 30 to the inputs 22 and 24 of the voltage comparator 20. In this way, it is possible to quickly and easily reverse the output polarity of the voltage comparator with respect to the input signal applied to the input terminal 32.
This does not appear to teach the particular arrangement for at least the second and third differential amps and their base input terminals biased to equal thresholds of opposite polarity to offset zero-crossing points if the second and third differential pair amps relative to a nominally zero-crossing point of the first differential pair amplifier. However, as discussed above, it is not clear how to interpret “substantially” in the claims.
US 5,359,652 (Mulder) at FIG. 2 illustrates a zero crossing detector including a differential amplifier 20.
PNG
media_image4.png
260
438
media_image4.png
Greyscale
See also the paragraphs in col. 4:
(7) The operation of the zero crossing detector as an offset voltage compensation circuit is as follows:
(8) In a first phase of the operation of the detector, switch 58 is closed and the non-inverting input 24 is connected to reference 26 via switch 58. The offset at the input is symbolically represented by means of a voltage source 60. In this phase also switch 32 is closed, so that the inverting input 22 is connected to output 30; and switch 48 is closed, as will be described below with respect to the threshold voltage. Since a feedback differential amplifier always tries to drive the two inputs to the same voltage, the offset voltage will now be present across capacitor 34. In the next phase switches 32, 48 and 58 are open and the switches 44 and 40 are closed. The charge of capacitor 34 will now partly flow to capacitor 36 which is charged as a result. In the next phase capacitor 34 is charged again to the offset voltage while the junction between capacitor 36 and open switch 40 is free from other connections so that the charge on capacitor 36 remains unaffected after which, in a next phase, again part of this offset voltage flows to capacitor 36. This process is continued until the whole offset voltage is present across capacitor 36. Assuming that no input signal is present on input 38, the side of capacitor 36 connected to the inverting input has been brought to the level of the offset voltage, and so has the inverting input. Because this is also the case with the non-inverting input, there is no longer a voltage difference between the two inputs and neither is there an offset effect any longer.
(10) The zero crossing detector according to the invention is arranged for producing a threshold voltage which, in addition, is reversed to a value of opposite sign once the input signal has exceeded the threshold voltage. This effect of hysteresis avoids that the detector is constantly reversed by a signal that remains in the neighbourhood of the threshold voltage for some time. The threshold voltage is produced as follows:
However, it does not appear to teach at least the three differential amplifiers as recited in the claims.
US 5,623,220 (Betti) at FIG. 2 illustrates a zero-crossing detector including first and second differential amps in series.
PNG
media_image5.png
64
360
media_image5.png
Greyscale
See also:
(10) By assuming the two stages G1 and G2 of the circuit of FIG. 2 are identical, they will have the same small signal gain Gj given by:
PNG
media_image6.png
46
142
media_image6.png
Greyscale
The equivalent input offset of the circuit will be given by the following expression:
PNG
media_image7.png
78
328
media_image7.png
Greyscale
(11) Notably, the offset of a differential pair of transistors depends primarily on the emitter area of the transistors and the biasing current. For example, in the case of an advanced CMOS process for high frequency, the dependence of the offset on the emitter area may be quantitatively derived from the curves of FIG. 4, which show the value of the standard deviation of the offset (.mu.V) as a function of the current density (.mu.A/.mu.m.sup.2) and respectively for a minimum emitter area (25 .mu.m.sup.2), for an emitter area equal to ten times (10.times.) the minimum area (250 .mu.m.sup.2) and for an emitter area equivalent to one hundred times (100.times.) the minimum emitter area (2500 .mu.m.sup.2). The same curves are shown in semilogarithmic form in FIG. 5, wherein the reference level 0 dB represents the offset of a minimum emitter area (25 .mu.m.sup.2) at low current density (which for the case shown is equivalent to 212 .mu.V).
However, it does not appear to teach at least the three differential amplifiers as recited in the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARREN WOLF whose telephone number is (571)270-3378. The examiner can normally be reached Monday through Friday, 7:00 AM to 3:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KENNETH N. VANDERPUYE can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DARREN E WOLF/Primary Examiner, Art Unit 2634
Prosecution Insights