DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are presented for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18/379,154 (i.e., now U.S. Patent No. 12,164,377).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-6 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,164,377.
For example, claim 1 of the present application teaches “A method for accessing a flash memory, comprising: using an initial gate voltage combination to read the flash memory to obtain first bit sequences; decoding the first bit sequences read from the flash memory; determining an electric charge distribution parameter corresponding to the initial gate voltage combination according to decoded information of the first bit sequences; determining a target gate voltage combination corresponding to the electric charge distribution parameter according a look-up table (LUT), wherein the target gate voltage combination comprises a plurality of threshold voltages; using the target gate voltage combination to read the flash memory to obtain second bit sequences; and decoding the second bit sequences to determine readout information of the flash memory”. Whereas claim 1 of U.S. PN: 12,164,377 teaches “A method for accessing a flash memory, comprising: using an initial gate voltage combination to read the flash memory to obtain first bit sequences; decoding the first bit sequences read from the flash memory; if the first bit sequences fail to be decoded, determining a target gate voltage combination according to a look-up table (LUT), wherein the target gate voltage combination comprises a plurality of threshold voltages; using the target gate voltage combination to read the flash memory to obtain second bit sequences; and decoding the second bit sequences to determine readout information of the flash memory; determining if the target gate voltage combination recorded in the LUT is no longer a best threshold voltage combination; and if it is determined that the target gate voltage combination recorded in the LUT is no longer the best threshold voltage combination, updating the plurality of threshold voltages of the target gate voltage combination in the LUT”.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the broader application claim would have been obvious in view of the narrower U.S. PN: 12,164,377. Therefore, claim 1 of the current application merely broadens the scope of the claim 1 of the U.S. PN: 12,164,377 by eliminating some limitations. It is obvious the limitations of claim 1 U.S. PN: 12,164,377 read on the limitations of claim 1 of the current application. Further, it has been held that the omission of an element and its function is an obvious expedient if the remaining elements perform the same functions as before. See In re Karlson, 136 USPQ 184 (CCPA 1963). Also note Ex parte Rainu, 168 USPQ 375 (BdPatApp&lnt 1970); omission of a reference element whose function is not needed would be obvious to one skilled in the art.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Independent claim 4 have corresponding issues with the independent claim 5 of '377 patent for the same rationales discussed above is also rejected under non-statutory obviousness-type double patenting.
Dependent claims of the instant application are deemed obvious over the dependent claims of '377 patent for the same rationales discussed above are also rejected under non-statutory obviousness-type double patenting.
.
Allowable Subject Matter
Claims 1-6 would be allowable if the applicant files Terminal Disclaimer to overcome the rejection(s) under obvious-type non-statutory double patenting, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Alhussien et al. (U.S. PN: 9,367,389) describes a method for applying a sequence of
sensing/read reference voltages in a read channel includes (A) setting a read window based on an
estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing
voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii)
a right-hand limit of the read window, and (iii) a point central to the read window, (C)
determining whether first, second and third reads are successful, and (D) if the first, second and
third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages
to values corresponding to different ones of (i) a point between the left-hand limit and the point
central to the read window and (ii) a point between the right-hand limit and the point central to
the read window.
Wu et al. (U.S. PN: 9,021,331) describe a method and apparatus for generating soft decision
error correction code information. The method includes generating or creating a lookup table
(LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision formation provided by the lookup table and assigned to the appropriate cells of the flash memory device.
Tai et al. (U.S. PN: 9,058,289) teach an error correction decoding to support the use
of flash memory or other storage mediums. More specifically, in some implementations,
a soft information generation system, method and/or device utilizes a pre-generated
collection of characterization vectors, for corresponding sets of storage medium
characterization parameter values, that includes soft information values for bit-tuples
that may be read from the storage medium. In some implementations, the soft
information is generated by a device characterization process for memory devices
produced by a particular manufacturing process, and stored in a characterization
module or look-up table. The characterization module or look-up table is indexed using
storage medium characterization parameter values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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/ESAW T ABRAHAM/ Primary Examiner,
Art Unit 2112