DETAILED ACTION
Response to Amendment
1. This written action is responding to the amendment dated on 05/25/2026.
2. The present application, filed on or after March 16, 2013, is being examined under
the first inventor to file provisions of the AIA .
3. Claims 1-2, 4-5, 7-8 and 11 are amended.
4. Objection to claims 4-6 and 10-12 is maintained.
5. Objection to claim 11 is withdrawn.
6. Claim interpretation under the 112(f) to claims 1, 2 and 7 is withdrawn.
7. Claims 1-13 are submitted for examination.
8. Claims 1-3, 7-9 and 13 are rejected.
9. The Examiner would like to point out that this action is made final (See MPEP
706.07a).
10.
Applicant’s Argument:
On pages 13-20 of the Remarks/Arguments, Applicant argues that the combination of Choi fails to teach: "the single multiplier is shared by the first encryption circuit and the second encryption circuit for both the first block cipher mode and the second block cipher mode".
Response to Argument:
Applicant’s arguments, filed on 05/25/2026, with respect to the rejections of claims 1, 3, 7-8 and 13 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn, However, upon further consideration, a new ground(s) of rejection for claims is made in view of (Nguyen et al. US 6,401,194).
11.
Allowable subject matter
Claims 4-6 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7-8 and 13 are rejected under 35 U.S.C. 103 as unpatentable over Choi et al. US 2011/0123020 (hereinafter Choi), and further in view of Nguyen et al. US 6,401,194 (hereinafter Nguyen).
Regarding claim 1 Choi teaches a flash memory controller, to be coupled between a host device and a flash memory device, comprising: a microcontroller [0156] and fig. 14; and
an encryption circuit, coupled to the microcontroller ([0135] and fig. 15), comprising:
a first encryption circuit, for encrypting a seed value to generate an encrypted seed value in a first block cipher mode according to a second key (Choi teaches encrypting a tweak value according to a second key [0016], [0053], fig. 2 and 8);
a second encryption circuit, for encrypting the seed value to generate an encrypted seed value in a second block cipher mode according to the second key ([0053], [0078], fig. 8);
a multiplier, coupled to the first encryption circuit and the second encryption circuit ([0052] and fig. 2), for multiplying the encrypted seed value, generated in the first block cipher mode or in the second block cipher mode, with a specific value αj according to a mode selection signal to generate a j-th multiplication result, α being a primitive element corresponding to a polynomial of a finite field multiplier (Choi teaches performing modular multiplication of the encrypted tweak value by a primitive value [0016]);
a first exclusive-OR (XOR) circuit, coupled to the multiplier, for performing a first XOR operation upon the j-th multiplication result and a j-th plaintext block to generate a first XOR result, a data unit sent from the host device and to be written into the flash memory device being received by the flash memory controller and including a sequence of plaintext blocks in which the j-th plaintext block is included (Choi teaches an encryptor inputs the consecutive data units to one of the encryption units in a mode, wherein each of the encryption units uses a block cipher protocol performing an exclusive OR (XOR) operation on a result value of the modular multiplication and an input data unit [0016], [0173-0174] and fig. 14-15);
a third encryption circuit, coupled to the first XOR circuit, for encrypting the first XOR result to generate an encrypted XOR result in the first block cipher mode according to a first key; a fourth encryption circuit, coupled to the first XOR circuit, for encrypting the first XOR result to generate the encrypted XOR result in the second block cipher mode according to the first key; and a second XOR circuit, coupled to the multiplier, the third encryption circuit, and the fourth encryption circuit, for performing a second XOR operation upon the j-th multiplication result and the encrypted XOR result which is generated in the first block cipher mode or in the second block cipher mode so as to generate a second XOR result as a j-th ciphertext block which is written into the flash memory device (Choi teaches a plurality of encryption units supporting an XTS encryption mode, the XTS encryption mode being an XOR-encrypt-XOR (XEX) encryption mode with tweak and ciphertext stealing, wherein a divider configured to divide a data stream into consecutive data units, and an allocator configured to allocate the divided data units to the encryption units, respectively, and to input the allocated data units to the encryption units. Each of the encryption units simultaneously processes the input data units [0017], [0173-0174], fig.7-10 and 14-15);
wherein the multiplier operating in the first block cipher mode or in the second block cipher mode is determined by either the mode selection signal generated from the microcontroller or the mode selection signal recorded in a 0-th plaintext block in the sequence of plaintext blocks (Choi an encryptor and encryption may use XTS mode of AES, which may apply to all types of block ciphers [0093], wherein the encryptor may controlled by a CPU, and wherein the CPU is part of a controller [0134-0135]). Choi does not teach a single multiplier is shared by a plurality of circuits. Nguyen substantially teaches a plurality of circuits may execute a plurality of instructions by employing a single-cycle multiplier (col. 2, lin. 58-61).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Choi such that the invention further includes a single multiplier is shared by a plurality of circuits. One would have been motivated to do so to reduce both cost and size of the processor (col. 2, lin. 58-66).
Regarding claim 3 Choi as modified teaches the flash memory controller of claim 1, wherein the first block cipher mode is associated with an operation for Advanced Encryption Standard, and the second block cipher mode is associated with another different cryptographic standard [0048].
Regarding claim 7 Choi as modified teaches the flash memory controller of claim 1, further comprising:
a decryption circuit, coupled to the microcontroller [0135], comprising:
a fifth encryption circuit, for encrypting the seed value to generate the encrypted seed value in the first block cipher mode according to the second key (Choi teaches encrypting a tweak value according to a second key [0016], [0053], fig. 2 and 8);
a sixth encryption circuit, for encrypting the seed value to generate the encrypted seed value in the second block cipher mode according to the second key ([0053], [0078], fig. 8);
another multiplier, coupled to the fifth encryption circuit and the sixth encryption circuit ([0052], fig. 2, and 7-9), multiplying the encrypted seed value, generated in the first block cipher mode or in the second block cipher mode, with the specific value αj according to the mode selection signal to generate another j-th multiplication result (Choi teaches performing modular multiplication of the encrypted tweak value by a primitive value [0016]);
a third XOR circuit, coupled to the another multiplier, for performing a third XOR operation upon the another j-th multiplication result and the j-th ciphertext block to generate a third XOR result, a data unit read from the flash memory device being received by the flash memory controller and including a sequence of ciphertext blocks in which the j-th ciphertext block is included (Choi teaches an encryptor inputs the consecutive data units to one of the encryption units in a mode, wherein each of the encryption units uses a block cipher protocol performing an exclusive OR (XOR) operation on a result value of the modular multiplication and an input data unit [0016], [0173-0174] and fig. 14-15);
a first decryption circuit, coupled to the third XOR circuit, for decrypting the third XOR result to generate a decrypted XOR result in the first block cipher mode according to the first key; a second decryption circuit, coupled to the third XOR circuit, for decrypting the third XOR result to generate the decrypted XOR result in the second block cipher mode according to the first key; and a fourth XOR circuit, coupled to the another multiplier, the first decryption circuit, and the second decryption circuit, for performing a fourth XOR operation upon the another j-th multiplication result and the decrypted XOR result which is generated in the first block cipher mode or in the second block cipher mode so as to generate a fourth XOR result as the j-th plaintext block which is decrypted from the j-th ciphertext block and is to sent to the host device (Choi teaches a first decryption data unit may decrypt a result value CC of the first XOR operator according to a first input key and AES encryption protocol. A second XOR operator may perform a bit-wise XOR operation on a decryption value PP of the first decryption data unit and the modular multiplication result value .tau.. Thus, plaintext P is output [0069], fig. 5, 11 and 16);
wherein the another multiplier operating in the first block cipher mode or in the second block cipher mode is determined by either the mode selection signal generated from the microcontroller or the mode selection signal recorded in a 0-th ciphertext block (Choi a endecryptor may use XTS mode of AES, which may apply to all types of block ciphers [0093], wherein the endecryptor may controlled by a CPU, and wherein the CPU is part of a controller [0134-0135]).
In response to Claim 8: Rejected for the same reason as claim 1
In response to Claim 13: Rejected for the same reason as claim 7
13.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as unpatentable over Choi and Nguyen as mentioned above, and further in view of Satpathyet et al. US 2020/0403774 (hereinafter Satpathy).
Regarding claim 2 Choi as modified teaches the flash memory controller of claim 1. Does not teach when operating in a first mode, a plurality of first encryption circuits are enabled while a plurality of second encryption circuits are disabled; and when operating in a second mode, the plurality of first encryption circuits are disabled while the plurality of second encryption circuits are enabled. Satpathy substantially teaches encryption engines enable or disable individual encryption or decryption circuits within a partitionable data path to dynamically and adaptively change encryption/decryption modes.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify Choi and Nguyen such that the invention further includes when operating in a first mode, a plurality of first encryption circuits are enabled while a plurality of second encryption circuits are disabled; and when operating in a second mode, the plurality of first encryption circuits are disabled while the plurality of second encryption circuits are enabled. One would have been motivated to do so to save power and make the system more efficient.
In response to Claim 9: Rejected for the same reason as claim 2
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ayoub Alata whose telephone number is (313) 446-6541. The examiner can normally be reached on M-F: 8:00am-4:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jay Kim can be reached at (571) 272-3804. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/AYOUB ALATA/Primary Examiner, Art Unit 2494
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