DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-9 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 5-9 recite the limitation "the one or more first metadata labels." There is insufficient antecedent basis for this limitation in the claims as claim 1 recites one or more first input metadata labels. Claim 3 is also rejected for it dependency on claim 2.
Claims 4, 5, 9 and 13 disclose input slot(s) and output slot(s), however, the claims fail to disclose what an input slot and output slot entails (e.g., such as slots or entries in a table, address/register locations, etc.). Therefore, the claims are rejected as being indefinite for failing to disclose what input slot(s) and output slot(s) entail.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sutherland et al. (U.S. PG Pub 2022/0092173; hereinafter Sutherland).
Regarding claim 1, Sutherland discloses a system comprising: processing hardware configured to ([0029] hardware system):
receive an input metadata pattern associated with an instruction executed by a host processor ([0047], [0093] receive a query with one or more inputs/input metadata pattern, such as an instruction type of the instruction, a tag, etc.), the input metadata pattern comprising:
one or more first input metadata labels associated with the instruction and/or a state of the host processor ([0113], [0114] one or more input metadata labels can be associated with an instruction); and
one or more second input metadata labels associated, respectively, with one or more registers used by the instruction and/or one or more memory locations referenced by the instruction ([0113], [0114] one or more input metadata labels can be associated with an application memory address for a load instruction, a data register for a store instruction, or a source address for a direct memory access instruction); and
generate an output metadata pattern, wherein: the one or more first input metadata labels are used to determine how to process the one or more second input metadata labels to generate the output metadata pattern ([0056], [0064], [0109], [0221], [0283] one or more outputs can be computed from the one or more input metadata labels based on the mapping of the inputs to the outputs for processing).
Regarding claim 2, Sutherland discloses the system of claim 1, wherein the processing hardware is configured to use the one or more first metadata labels to look up a transformation to be applied to a bit string obtained from the one or more second input metadata labels ([0175], [0190]-[0194]).
Regarding claim 3, Sutherland discloses the system of claim 2, wherein the transformation comprises a mask ([0175], [0190]-[0194], [0219]-[0221]).
Regarding claim 4, Sutherland discloses the system of claim 1, wherein the one or more first input metadata labels are associated, respectively, with one or more first input slots; and the one or more second input metadata labels are associated, respectively, with one or more second input slots ([0115], Figure 4).
Regarding claim 5, Sutherland discloses the system of claim 4, wherein the processing hardware is configured to use the one or more first metadata labels to selectively disable at least one second input slot of the one or more second input slots ([0175], [0190]-[0194]).
Regarding claim 6, Sutherland discloses the system of claim 1, wherein the processing hardware is configured to use the one or more first metadata labels to selectively activate at least one hardware block of a plurality of hardware blocks configured to process information obtained from the one or more second input metadata labels ([0112]-[0116]).
Regarding claim 7, Sutherland discloses the system of claim 1, wherein the processing hardware is configured to use the one or more first metadata labels to configure a hardware block for processing information obtained from the one or more second input metadata labels ([0110], [0111]).
Regarding claim 8, Sutherland discloses the system of claim 7, wherein the hardware block is configured to apply a selected operation to one or more bit strings obtained from the one or more second input metadata labels; and the operation is selected, based on the one or more first metadata labels, from a plurality of operations on bit strings ([0028], [0041], [0047], [0111], [0263]).
Regarding claim 9, Sutherland discloses the system of claim 7, wherein the output metadata pattern comprises at least one output metadata label; the hardware block is configured to generate, based on the information obtained from the one or more second input metadata labels, the at least one output metadata label; and the processing hardware is further configured to: use the one or more first metadata labels to select at least one output slot from a plurality of output slots; and provide the at least one output metadata label to the at least one selected output slot ([0054], [0119]).
Regarding claim 10, Sutherland discloses the system of claim 1, wherein the processing hardware comprises a policy check function block configured to provide, based on the one or more first input metadata labels and/or the one or more second input metadata labels, an indication of whether the instruction is allowed according to one or more policies ([0041], [0048]-[0050]).
Regarding claim 11, Sutherland discloses the system of claim 10, wherein the processing hardware further comprises a conversion block configured to convert the one or more first input metadata labels and/or the one or more second input metadata labels into one or more third input metadata labels; and the policy check function block is configured to receive, as input, the one or more third input metadata labels ([0142], [0306]).
Regarding claim 12, Sutherland discloses the system of claim 11, wherein the conversion block comprises an expansion block configured to convert bit strings of length N’ into bit strings of length N, where N > N’ ([0039], [0214], [0284]-[0288]).
Regarding claim 13, Sutherland discloses the system of claim 10, wherein: the output metadata pattern comprises one or more output metadata labels; and the processing hardware further comprises an output function block configured to provide, based on the one or more first input metadata labels and/or the one or more second input metadata labels, the one or more output metadata labels to one or more respective output slots ([0054], [0119]).
Regarding claim 14, Sutherland discloses the system of claim 1, wherein: the one or more first input metadata labels are used to determine how to process the one or more first input metadata labels and the one or more second input metadata labels to generate the output metadata pattern ([0056], [0064], [0109], [0221], [0283]).
Regarding claim 15, Sutherland discloses the system of claim 1, wherein the processing hardware comprises one or more programmable logic devices programmed by bitstreams ([0120]).
Regarding claim 16, Sutherland discloses the system of claim 1, wherein the processing hardware comprises one or more logic circuits fabricated into semiconductors ([0321]).
Claims 17 and 18 contain corresponding limitations as claim 1 and are therefore rejected for the same rationale.
Support for Amendments and Newly Added Claims
Applicants are respectfully requested, in the event of an amendment to claims or submission of new claims, that such claims and their limitations be directly mapped to the specification, which provides support for the subject matter. This will assist in expediting compact prosecution and reducing potential 35 USC § 112(a) or 35 USC § 112, 1st paragraph issues that can arise when claims are amended. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.121(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient. The examiner thanks the Applicant in advance for providing support for any amendments or newly added claims.
Examiner cites particular columns and line numbers or paragraphs in the references as applied to claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may be applied as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Boling (US 2021/0042100): Translating mapping policy into code;
DeHon (US 2017/0177368): Techniques for metadata processing;
Milburn (WO 2021178493 A1): Caching Metadata.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIEDRA M MCQUITERY whose telephone number is (571)272-9607. The examiner can normally be reached Monday - Thursday, 8 am - 6 pm (C.S.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sanjiv Shah can be reached at (571)272-4098. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Diedra McQuitery/Primary Examiner, Art Unit 2166