DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Darwhekar et al. (US 11500336).
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With respect to claim 1, figure 3 of Darwhekar et al. discloses a signal sampling device, comprising: an input circuit (202), activated in a first period according to a first clock signal (101 generates clock signals P1-P2, the first clock being P1 or P2bar) to generate a plurality of first output signals (119 based on P1) according to a plurality of input signals (P1 – DAC_LOAD and RST); and a first latch circuit (110), activated in a second period according to a second clock signal (P2 or P1bar) to generate a plurality of second output signals (119 based on P2) according to the plurality of first output signals, wherein the second period is later than the first period, wherein a period in which the input circuit resets the plurality of first output signals (119s) and the second period partially overlap (during intermediate signal period). (Here, period is an arbitrary time and in the course of the comparison produced by setting the output signals (period of resetting the plurality of output signals) happens also at or produced at the same time edge controller 110 is set and thus happen or produce the result of the output signals 119 at an overlapping intermediate period.)
With respect to claim 2, Darwhekar et al. discloses the signal sampling device according to claim 1, wherein the first period and the second period have a same time length. (Here, the clocking signals P1 and P1bar would be the same length and P2 and P2bar would be the same length based on the same division as they are inverted outputs of each other. Ostensibly it would also be within the scope to choose the same lengths of all the divided signals)
With respect to claim 3, Darwhekar discloses the signal sampling device according to claim 1, wherein when the input circuit starts to reset (based on dynamic reset comparator) levels of the plurality of first output signals (119s) according to the first clock signal (P1 or P2 bar), the first latch circuit starts to generate the plurality of second output signals (subsequent different 119s).
With respect to claim 5, Darwhekar discloses the signal sampling device according to claim 1, wherein the first period and the second period partially overlap. (during intermediate signal period).
With respect to claim 6, Darwhekar discloses the signal sampling device according to claim 1, further comprising: a logic gate circuit (Mux 112 would be consigned a logic gate), generating a plurality of third output signals (119 based on select line) according to the plurality of second output signals (different 119 fed back to oscillator) and a third clock signal (clock signal based on 101 and possibly feedback signal).
With respect to claim 7, Darwhekar discloses the signal sampling device according to claim 6, further comprising: a second latch circuit (see fig. 6, wherein the dynamic latch is comprised of multiple latches each of which would generate the output 119), generating a plurality of fourth output signals (different 119s) according to the third clock signal (clock signals based on oscillator) and the plurality of third output signals (119s).
With respect to claim 8, Darwhekar discloses the signal sampling device according to claim 7, further comprising: a corrector (comparator 204), correcting, according to one of the plurality of fourth output signals (fourth output signals 119 feedback to produce appropriate clocks and PI output signals), levels of a plurality of nodes in the input circuit (nodes such as the phase interpolator nodes would suffice to produce the first output signals) that are used to output the plurality of first output signals.
With respect to claim 9, Darwhekar discloses the signal sampling device according to claim 8, wherein the corrector comprises: a digital control circuit (124), generating a digital code according to the one of the plurality of fourth output signals (iterative 119); and a digital-to-analog converter (DAC) (208), generating a plurality of reference voltages (PIout) according to the digital code so as to correct the levels of the plurality of nodes.
With respect to claim 10, Darwhekar discloses the signal sampling device according to claim 6, wherein the third clock signal (i.e. clock signal generated from 101, i.e. P1bar) , the second clock signal (P2) and the first clock signal (P1) have a same cycle. (It is within the scope of the invention to set the clock signals as such so they operate on the same cycle).
Response to Arguments
Applicant's arguments filed 4/13/2026 have been fully considered but they are not persuasive.
With respect to applicant’s argument P1-DAC_LOAD, and RST are control signals not input sigals, the Examiner disagrees as they are input into 208.
With respect to applicant’s argument no plurality of output signals are from 202 alone, the Examiner disagrees. From 202 alone comes an output signal at 205 and another output signal into comparator 204. These in turn produce the output signals at 119. Because the circuit is iterative 119 is multiple output signals being produced based on the selection at 112. Also because 202 is multiple circuits, they produce multiple signals.
With respect to the period of reset overlaps the second period, the Examiner points out period is an arbitrary time and in the course of the comparison produced by setting the output signals (period of resetting the plurality of output signals) happens also at or produced at the same time edge controller 110 is set and thus happens or produces the result of the output signals 119 at an overlapping intermediate period.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mentatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849 /Menatoallah Youssef/SPE, Art Unit 2836
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