DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Switched Mode Power Supply (SMPS) and the output inductor (see claims 1, 9 and 18) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1, lines 12 and 14 recites “the inductor”, which should be –the output inductor—because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 3 is objected to because of the following informalities: Claim 3, line 2 recites “an output voltage”, which should be --the output voltage -- because this term was previously presented in the claim; Claim 3, line 3 recites “a reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim 4 is objected to because of the following informalities: Claim 4, line 8 recites “the reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim 11 is objected to because of the following informalities: Claim 11, line 3 recites “an output voltage”, which should be --the output voltage -- because this term was previously presented in the claim; Claim 11, line 3 recites “a reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim 12 is objected to because of the following informalities: Claim 12, line 7 recites “the reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 3, line 4 recites “an output voltage”, which should be --the output voltage -- because this term was previously presented in the claim; Claim 3, line 4 recites “a reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim 20 is objected to because of the following informalities: Claim 20, line 6 recites “the reference output voltage”, which should be --the reference voltage -- because in this term way was previously presented this term in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9-12 and 15-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yamada et al. (US 10,720,839), hereinafter Yamada.
Regarding claim 1, Yamada discloses (see figures 1-12) a Switched Mode Power Supply (SMPS) (figure 3, part 300) comprising: a switching stage (figure 3, part 110/120/130) having a high-side switch (figure 3, part 110), a low-side switch (figure 3, part 120), and an output inductor (figure 3, part 130) (column 3; lines 62-67; switching converter such as a DC-DC buck converter); and control circuitry (figure 3, part control circuitry 140-370) that operates the high-side switch (figure 3, part 110) and the low-side switch (figure 3, part 120) based on a clock signal (figure 3, part clock signal generated by RLIM), wherein the control circuitry (figure 3, part control circuitry 140-370) is configured to: detect (figure 3, part through 162) that an output voltage of the switching stage (figure 3, part VOUT) deviates (figure 3, part through 164) from a reference voltage (figure 3, part VREF) (column 4; lines 1-15; an error amplifier 164), enable negative valley regulation (figure 3, part 370)(figures 6B and 7, part enable negative valley regulation at light load, when VEA is lower than VRB) after the detecting (figure 3, part through VEA input to 370 as indication signal for reverse current request) that the output voltage (figure 3, part VOUT) deviates from the reference voltage (figure 3, part VREF) (column 6; lines 14-54; The adaptive reverse current limit generator 370 has an input for receiving one or more indication signals from the voltage to pulse width converter 350 and an output for providing an adjusted voltage reference limit VRLIM. The nature of the indication signals may vary depending on the implementation of the adaptive reverse current limit reference generator 370. For instance, the indication signals may include various signals either received by the voltage pulse width converter 350 or provided by the voltage pulse width converter 350. For example, the indication signals may include the amplified error voltage VEA provided by the error amplifier… In operation, when the DC-DC converter 300 is operating in light load conditions, the reverse current is adjusted to the amount required for regulating the output voltage), upon enabling the negative valley regulation (figure 3, part 370) (figures 6B and 7, part enable negative valley regulation at light load, when VEA is lower than VRB), detect (figure 3, part 180; through LX) that a current flowing through the inductor (figure 3, part IL through 130) falls below a threshold (figure 3, part threshold generated by VRLIM) (columns 5 and 6; lines 59-67 and 1-8; In order to maximise the efficiency of the DC-DC converter in light-load conditions, the synchronous rectifier switch 120 should be turned off just before the inductor current IL becomes negative. In the description the current flowing from the output node towards the switching node LX is referred to as the reverse current. The reverse current limit signal generator 180 compares the voltage VLX at the switching node with the limit reference voltage VRLIM provided by the reverse current limit reference generator 170, to generate the reverse limit signal RLIM. When the output stage controller 140 receives the reverse current limit signal RLIM, it stops the reverse current by turning off (open) the synchronous rectifier 120), and initiate a next clock cycle of the clock signal (figure 3, part initiate a next clock cycle of clock signal generated by RLIM) once the current flowing through the inductor (figure 3, part IL through 130) is detected (figure 3, part 180; through LX) to fall below the threshold (figure 3, part threshold generated by VRLIM) (column 6; lines 1-8; The reverse current limit signal generator 180 compares the voltage VLX at the switching node with the limit reference voltage VRLIM provided by the reverse current limit reference generator 170, to generate the reverse limit signal RLIM. When the output stage controller 140 receives the reverse current limit signal RLIM, it stops the reverse current by turning off (open) the synchronous rectifier 120) (column 8; lines 31-39; In light load conditions, for instance for a load current between 0 mA and 4 mA, the peak of the inductor current is function of the minimum pulse width of the DC-DC converter. The valley of the inductor current corresponding to the amount of reverse current, is adjusted depending on the amplified error voltage VEA, in order to maintain the regulation of the output voltage VOUT).
Regarding claim 2, Yamada discloses everything claimed as applied above (see claim 1). Further, Yamada discloses (see figures 1-12) the control circuitry (figure 3, part control circuitry 140-370) is configured to set the threshold (figures 3 and 5A, part threshold generated by VRLIM; through 510).
Regarding claim 3, Yamada discloses everything claimed as applied above (see claim 2). Further, Yamada discloses (see figures 1-12) the control circuitry (figure 3, part control circuitry 140-370) is configured to set the threshold (figures 3 and 5A, part threshold generated by VRLIM; through 510) by determining (figures 3 and 5A, part through VEA) a difference (figure 3, part 164) between an output voltage of the switching stage (figure 3, part VOUT; through VFB) and a reference output voltage (figure 3, part VREF).
Regarding claim 4, Yamada discloses everything claimed as applied above (see claim 3). Further, Yamada discloses (see figures 1-12) the control circuitry (figure 3, part control circuitry 140-370) further comprises: a low-side sense switch (figure 5A, part low-side sense switch at 530) (column 7; lines 40-46; the resistive component 530 may be a resistor or a transistor having an on-resistance that matches the on-resistance of the synchronous rectifier 120); and a current source (figures 5A and 5B, part current source that generates IA), wherein the current source (figures 5A and 5B, part current source that generates IA) is configured to provide a current (figures 5A and 5B, part IA) to the low-side sense switch (figure 5A, part low-side sense switch at 530), wherein the current (figures 5A/5B and 6B, part IA) is proportional to the difference (figures 5A/5B and 6B, part VEA) between the output voltage of the switching stage (figures 3 and 5A/5B, part VOUT) and the reference output voltage (figures 3 and 5A/5B, part VREF), and wherein the threshold is a voltage (figures 3 and 5A/5B, part threshold generated by VRLIM) over the low sense switch (figure 5A, part low-side sense switch at 530) caused by the current (figures 5A and 5B, part IA) (column 7; lines 31-64).
Regarding claim 7, Yamada discloses everything claimed as applied above (see claim 1). Further, Yamada discloses (see figures 1-12) the SMPS (figure 3, part 300) is at least one selected from the group consisting of: a buck converter, a boost converter, a buck-boost converter, a cuk converter, a flyback converter, and a forward converter (figure 3, part 300) (column 1; lines 14-17; Switching converters such as buck, boost or buck-boost converters).
Regarding claim 9, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 10, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 11, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 12, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 15, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 16, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 17, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 19, claims 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 20, claims 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 8, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (US 10,720,839), hereinafter Yamada, in view of Yao (US 2020/0336069).
Regarding claim 5, Yamada discloses everything claimed as applied above (see claim 4). Further, Yamada discloses (see figures 1-12) the high-side switch (figure 3, part 110), the low- side switch (figure 3, part 120), and the low-side sense switch (figure 5A, part low-side sense switch at 530) (column 7; lines 40-46; the resistive component 530 may be a resistor or a transistor having an on-resistance that matches the on-resistance of the synchronous rectifier 120). However, Yamada does not expressly disclose Field-Effect Transistors (FET).
Yao teaches (see figures 1-8) the high-side switch (figure 3, part HS), the low- side switch (figure 3, part LS), and the low-side sense switch are Field-Effect Transistors (FET) (figure 3, part LSs).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switches of Yamada with the FET features as taught Yao, because it provides more efficient switching operation.
Regarding claim 6, Yamada discloses everything claimed as applied above (see claim 5). Further, Yamada discloses (see figures 1-12) the low-side switch (figure 3, part 120) and the low-side sense switch are a same type (figure 5A, part low-side sense switch at 530) (column 7; lines 40-46; the resistive component 530 may be a resistor or a transistor having an on-resistance that matches the on-resistance of the synchronous rectifier 120). However, Yamada does not expressly disclose FET.
Yao teaches (see figures 1-8) the low-side switch (figure 3, part LS) and the low-side sense switch are a same type of FET (figure 3, part LSs).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the switches of Yamada with the FET features as taught Yao, because it provides more efficient switching operation.
Regarding claim 8, Yamada and Yao teach everything claimed as applied above (see claim 5). Further, Yamada discloses (see figures 1-12) the SMPS (figure 3, part 300) is at least one selected from the group consisting of: a buck converter, a boost converter, a buck-boost converter, a cuk converter, a flyback converter, and a forward converter (figure 3, part 300) (column 1; lines 14-17; Switching converters such as buck, boost or buck-boost converters).
Regarding claim 13, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 14, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
Prosecution Insights