Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant’s filing on 25th October 2024. Claims 1-20 are presently pending and under consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25th June 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 8868825. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of US 8868825. For example:
Instant Application
US 8868825
Claim 1. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises a plurality of solid state storage drives;
Claim 1. A method of applying an address space in a non-volatile solid-state storage, comprising: receiving user data for storage in the non-volatile solid-state storage;
assigning to a first portion of the plurality of portions of the user data, a first address of a plurality of non-repeating addresses of an address space;
translating a first address of a portion of the user data in a first address space, to a second address of the portion of the user data in a second address space, wherein addresses in the second address space have a range and a sequence, each address in the second address space applied in keeping with the sequence to a portion of the user data in the non-volatile solid-state storage is different at a time of application from all addresses in the second address space previously applied in keeping with the sequence in the non-volatile solid-state storage to portions of the user data, and the range of the addresses in the second address space is greater than a maximum number of addresses in the second address space expected to be applied during a lifespan of the non-volatile solid-state storage;
and writing each of the plurality of portions of data to respective storage drive.
and storing the portion of the user data in the non-volatile solid-state storage, with the portion of the user data associated with both the first address and the second address, wherein at least one method operation is performed by a processor.
Claim 1 and similarly claims 11 and 20 of the instant application and claims 1, 8, and 15 of US Patent 8868825 differ only in slight wording changes and accordingly, claims 1, 11, and 20 of the instant application are fully disclosed and anticipated by the limitations recited in claims 1, 8 and 15 of US 8868825. Additionally, the dependent claims 2-10 and 12-19 of the instant application are anticipated by other ones of the dependent claims of US Patent 8868825, having similar limitations or only differing by grammatical wording changes.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10114757. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of US 10114757. For example:
Instant Application
US 10114757
Claim 1. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises a plurality of solid state storage drives;
Claim 8. A method of applying an address space to data storage, comprising: distributing user data throughout a plurality of storage nodes, each of the plurality of storage nodes having non-volatile solid-state memory for user data storage; receiving a plurality of portions of user data for storage in the non-volatile solid-state memory;
assigning to a first portion of the plurality of portions of the user data, a first address of a plurality of non-repeating addresses of an address space;
assigning a non-overlapping range of an address space to each of the storage nodes wherein addresses in the address space have a range that exceeds application of addresses in a lifespan of the storage nodes, and wherein a range of addresses in the address space is assigned to each of the storage nodes; assigning to each successive one of the plurality of portions of user data an address in the second address space;
and writing each of the plurality of portions of data to respective storage drive.
and writing each of the plurality of portions of user data to the non-volatile solid-state memory.
Claim 1 and similarly claims 11 and 20 of the instant application and claim 8 of US Patent 10114757 differ only in slight wording changes, accordingly, claims 1, 11, and 20 of the instant application are fully disclosed and anticipated by the limitations recited in claim 8 of US 10114757. Additionally, the dependent claims of the instant application are anticipated by other ones of the dependent claims of US Patent 10114757, having similar limitations or only differing by minor grammatical wording changes.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10372617. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of US 10372617. For example:
Instant Application
US 10372617
Claim 1. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises a plurality of solid state storage drives;
Claim 8. A method of applying an address space to data storage, comprising: distributing user data throughout a plurality of storage nodes through erasure coding; receiving a plurality of portions of user data for storage in the non-volatile solid-state memory, each portion associated with an authority having ownership for respective portion;
assigning to a first portion of the plurality of portions of the user data, a first address of a plurality of non-repeating addresses of an address space;
assigning to each successive one of the plurality of portions of user data one of a plurality of sequential, nonrepeating addresses of an address space, the sequential, nonrepeating addresses having a range that exceeds application of the sequential, nonrepeating addresses in a lifespan of the non-volatile solid-state memory;
and writing each of the plurality of portions of data to respective storage drive.
and writing each of the plurality of portions of user data to memory such that each of the plurality of portions of user data is identified and locatable for reading via the one of the plurality of sequential, nonrepeating addresses of the address space.
Claim 1 and similarly claims 11 and 20 of the instant application and claim 8 of US Patent 10372617 differ only in slight wording changes, accordingly, claims 1, 11, and 20 of the instant application are fully disclosed and anticipated by the limitations recited in claim 8 of US 10372617. Additionally, the dependent claims of the instant application are anticipated by other ones of the dependent claims of US Patent 10372617, having similar limitations or only differing by minor grammatical wording changes.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10817431. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of US 10817431. For example:
Instant Application
US 10817431
Claim 1. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises a plurality of solid state storage drives;
Claim 2 (The method of claim 1) 1. A method of applying an address space in a non-volatile solid-state storage, comprising: receiving user data for storage in the non-volatile solid-state storage;
assigning to a first portion of the plurality of portions of the user data, a first address of a plurality of non-repeating addresses of an address space;
and translating a first address of a portion of the user data in a first address space, to a second address of the portion of the user data in a second address space, wherein addresses in the second address space have a range, the range of the addresses in the second address space is greater than a maximum number of addresses in the second address space expected to be applied during a lifespan of the non-volatile solid-state storage, and wherein the portion of the user data is associated with both the first address and the second address
and writing each of the plurality of portions of data to respective storage drive.
wherein storing the portion of the user data in the non-volatile solid- state storage includes: writing the portion of the user data to non-volatile random access memory (NVRAM) of the non-volatile solid-state storage; and transferring the portion of the user data from the NVRAM to flash memory of the non- volatile solid-state storage.
Claim 1 and similarly claims 11 and 20 of the instant application and claim 2 of US Patent 10372617 differ only in slight wording changes, accordingly, claims 1, 11, and 20 of the instant application are fully disclosed and anticipated by the limitations recited in claim 2 of US 10372617. Additionally, the dependent claims of the instant application are anticipated by other ones of the dependent claims of US Patent 10372617, having similar limitations or only differing by minor grammatical wording changes.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12135654. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of US 12135654. For example:
Instant Application
US 12135654
Claim 1. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises a plurality of solid state storage drives;
Claim 8. A method, comprising: receiving a plurality of portions of user data for storage into a storage system wherein the storage system comprises solid state storage drives having non-uniform storage capacity
assigning to a first portion of the plurality of portions of the user data, a first address of a plurality of non-repeating addresses of an address space;
assigning to each of the plurality of portions of user data one of a plurality of non- reused addresses of an address space, the address space having a range that exceeds application of addresses in a lifespan of non-volatile solid-state memory of a storage drive, the assigning performed through a processing device, wherein the plurality of non- reused addresses are not repeated in the storage system during the lifespan of the non- volatile solid-state memory;
and writing each of the plurality of portions of data to respective storage drive.
writing each of the plurality of portions of data to respective storage drive; generating snapshots of the user data, wherein the snapshots record previous addresses associated with previous versions of the user data; and restoring a previous version of the data based on one or more non-repeating addresses in the address space.
Claim 1 and similarly claims 11 and 20 of the instant application and claim 8 of US Patent 12135654 differ only in slight wording changes, accordingly, claims 1, 11, and 20 of the instant application are fully disclosed and anticipated by the limitations recited in claim 8 of US 12135654. Additionally, the dependent claims of the instant application are anticipated by other ones of the dependent claims of US Patent 12135654, having similar limitations or only differing by minor grammatical wording changes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “optimized” in claims 2 and 12 is a relative term which renders the claim indefinite. The term “optimized” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The specification recites the term “optimized” in three places and provides no clarification about how optimization occurs or what is necessary to achieve optimization. For purposes of examination, the term “optimized” has been interpreted to mean compatible with solid state storage/memory/flash.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Independent claims 1, 11, and 20 and dependent claims 2-9 and 12-18 are rejected under 35 USC 101 because the claimed invention is directed to a judicial exception of an abstract idea without significantly more. The claims recite a method of assigning an address from a plurality of non-repeating addresses of an address space, as in independent claims 1, 11, and 20.
The limitations of assigning an address from a plurality of non-repeating addresses of an address space, as in claims 1, 11, and 20, under its broadest reasonable interpretation, covers performance of the limitations entirely in the mind but for the recitation of generic computer components (i.e. storage system, solid state storage drives, a processing device, a non-transitory computer readable storage medium). That is, other than reciting storage system, solid state storage drives, a processing device, nothing in the claim elements precludes the steps from practically being performed in the mind. In this instance, an address is assigned from a plurality of non-repeating addresses of an address space. If a claim limitation under its broadest reasonable interpretation covers performing of the limitation in the mind but for the recitation of generic computer components, then it falls within the “mental processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, claim 1 recites the additional elements of “a storage system” “a plurality of solid state storage drives”, a “receiving” step, a “writing” step, claim 11 recites the additional elements of “a storage system”, “a plurality of solid state storage drives”, “a processing device”, a “receive” step, and a “write” step and claim 20 recites the additional elements of “a non-transitory computer readable storage medium”, “a processing device”, “a storage system”, “a plurality of solid state storage drives”, a “receive” step, and a “write” step , which are recited at a high level of generality (i.e. generic computer components performing generic computer functions), such that they amount to no more than mere instructions to apply the exception using generic computer components. The additional elements of the “receive” and “write” step of claims 1 and 20 and “receiving” and “writing” step of claim 11 are mere data gathering and output which amounts to insignificant extra-solution activity (See MPEP 2106.05(g)). Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on performing the abstract idea entirely in the mind.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a storage system” “a plurality of solid state storage drives”, as in claim 1, the additional elements of “a storage system”, “a plurality of solid state storage drives”, “a processing device”, as in claim 11, and the additional elements of “a non-transitory computer readable storage medium”, “a processing device”, “a storage system”, “a plurality of solid state storage drives”, as in claim 20, amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Further, the additional elements of the “receive” and “write” steps of claims 1 and 20 and “receiving” and “writing” steps of claim 11 are directed to “receiving or transmitting data over a network” and “storing and retrieving information in memory”, which the courts have found to be well-understood, routine, and conventional activities (See MPEP 2106.05(d)(II)). Thus the claims are not patent eligible.
Additionally, dependent claims 2-9 and 12-18 recite “assigning”, “assigning”, “assigning”, “assigning”, “tracking”, “translating”, “erasing” steps that covers performance of the limitation entirely in the mind but for the recitation of generic computer components, or else include additional functional elements which do not provide a practical application of the mental process. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception and therefore are also patent ineligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Manning (How Yaffs works, Applicant supplied NPL, 1st June 2012, hereinafter NPL1) in view of Manning (Yaffs Sequence number overflow?, Applicant supplied NPL, hereinafter NPL2).
Regarding claims 1, 11, and 20, taking claim 11 as exemplary, NPL1 discloses a storage system, comprising: a plurality of solid state storage drives (See NPL1, section 6, a system may have two NAND chips in parallel, each chip acting as a “drive”); and
a processing device operatively coupled to the plurality of solid state storage drives (See NPL1, Section 2, “Yaffs has been used with multiple different CPUs), the processing device configured to:
receive a plurality of portions of user data for storage into the storage system (See NPL1, Section 7, “file system data is written…can hold one of two types of chunk: Data chunk”);
assign to a first portion of the plurality of portions of the user data, a first address of a plurality of addresses of an address space (See NPL1, Section 10, disclosing a sequence number, “each block is allocated, the file system’s sequence number is incremented and each chunk in the block is marked with that sequence number”); and
write each of the plurality of portions of data to respective storage drive (See NPL1, Section 5, disclosing objects are stored in the file system).
NPL1 does not disclose the plurality of addresses are non-repeating addresses.
However, NPL2 discloses the plurality of addresses are non-repeating addresses (See NPL2, page 1 disclosing YAFFS2 utilizing a 4 byte sequence number to differ older chunks from the latest one and resulting in a 18 year lifespan, or longer than the device will be used before repeating).
NPL1 and NPL2 are analogous art directly disclosing principles of YAFFS2 file system operation. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the YAFFS2 storage system of NPL1 with the large address sequencing of NPL2 as the 4byte sequence number/addressing is a fundamental principal of operation of YAFFS2.
Regarding claims 2 and 12, taking claim 12 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 11 as above. NPL1 further discloses wherein the address space is optimized for solid state memory (See NPL1, Section 2, disclosing “a flash file system designed from the ground up to work with NAND flash”).
Regarding claims 3 and 13, taking claim 13 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claims 12 as above. NPL1 further discloses assigning to the first portion of the plurality of portions of the user data, a second address of the plurality of non-repeating addresses (See NPL1, Section 10, disclosing a sequence number, “each block is allocated, the file system’s sequence number is incremented and each chunk in the block is marked with that sequence number”), wherein the address space includes a segment address space and wherein the second address is included in the segment address space (See NPL1, section 7 & 10, disclosing a sequential order of chunks, each of the chunks having a chunkID).
Regarding claims 4 and 14, taking claim 14 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 13 as above. NPL1 further discloses assigning to the first portion of the plurality of portions of the user data, a third address of the plurality of non-repeating addresses (See NPL1, Section 10, disclosing a sequence number, “each block is allocated, the file system’s sequence number is incremented and each chunk in the block is marked with that sequence number”), wherein the address space includes a virtual allocation unit address space and wherein the third address is included in the virtual allocation unit address space (See NPL1, Section 10, disclosing blocks, or virtual allocation units, comprised of chunks, which are sequentially written and which has incremented sequence numbers as each chunk in the block is written and marked, see also, Section 7, disclosing example blocks 1 and 2, each comprised of a number of chunks, each chunk having a chunk Id).
Regarding claims 5 and 15, taking claim 15 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 14 as above. NPL1 further discloses assigning to the first portion of the plurality of portions of the user data, physical flash memory location based on the third address (See NPL1, Section 6, disclosing NAND flash arranged in pages for programming, erasure in blocks, where Yaffs unit allocation of a chunk typically same as a NAND page and Section 10, disclosing blocks, or virtual allocation units, comprised of chunks, which are sequentially written).
Regarding claims 6 and 16, taking claim 16 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 14 as above. NPL1 further discloses tracking the first address, the second address, and the third address in a plurality of address translation tables (See NPL1, Section 5, disclosing YAFFS storage of inodes and directory entires, where an inode may also be a file or directory, and directory entries providing the naming mechanism that is used to locate inodes, or in other words, translation tables for addresses as the inodes are a per-file system unique number that identifies an associated object (see Section 12.4)).
Regarding claims 7 and 17, taking claim 17 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 11 as above. NPL1 further discloses translating file paths of the plurality of portions of the user data to inode identifiers (IDs) of the plurality of portions of user data (See NPL1, Section 12.4, “the inode number is a per-file system unique number that identifies the object”, or in other words, inode IDs translate to the file system paths in order to reach the user data).
Regarding claim 8, NPL1 in view of NPL2 disclosed the method of claim 1 as above. NPL1 further discloses wherein an inode ID identifies an authority having ownership for the respective portion of the user data (See NPL1, Section 5, disclosing object storage in Yaffs, with each object identified with an integer object ID and Section 12.4, further disclosing objects having one name and the inode number of the object is the unique number identifying the object).
Regarding claims 9 and 18, taking claim 18 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 11 as described hereinabove. NPL1 further discloses erasing a block of pages of a solid state storage drive, wherein writing each of the plurality of portions of user data comprises writing individual pages in an order within a single erased block according to the plurality of non-repeating addresses of the address space (See NPL1, Section 6, disclosing NAND flash arranged in pages for programming, erasure in blocks, where Yaffs unit allocation of a chunk typically same as a NAND page, chunks forming a block and Section 7, disclosing writing is performed sequentially, or in other words, “in an order within a single erased block”).
Regarding claim 10 and 19, taking claim 19 as exemplary, NPL1 in view of NPL2 disclosed the storage system of claim 11 as above. NPL1 further discloses generating snapshots of the user data, wherein the snapshots record previous addresses associated with previous versions of the user data; and restoring a previous version of the data based on one or more non-repeating addresses in the address space (See NPL1, Section 13.4, disclosing checkpointing using snapshots of the Yaffs runtime state and used to reconstitute the runtime state).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (1) Ramsundar et al (US 2014/0325115 A1) disclosing a memory controller with a storage management layer managing a logical address space with logical addresses for referencing memory resources using a universally unique identifier.
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/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137