DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1- 5, 7-11, 13-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20240223296 A1, hereinafter Chen) in view of Yang et al. (US 20180191802 A1, hereinafter Yang).
Claim 1: Chen teaches A method comprising (abstract): determining a first multiframe that bears data at a first location in a packet (Fig. 3, element 306, Fig. 5, element 506, Ethernet Frame is reading as a first multiframe, [0057-0058], start location of Ethernet frame 306 is reading as first location, which can be calculated by combining Tref with ΔTX and Δ TX_SFD);
determining a real timestamp of the first multiframe (Fig. 3, Fig. 5, Ethernet Frame) based on a first timestamp of a second multiframe (Fig. 3, element reference frame or PHY Frame 206(N), Fig. 5, element PHY Frame 404(0), Fig.9, first frame) in a channel in which the first multiframe is located (Fig. 3, Fig. 5, Fig. 9, [0095], disclose generating a timestamp
responsive to detecting the first frame, the adjusting of the timestamp may include determining an offset between the SFD of the packet and the beginning of the first frame, wherein the adjusted timestamp is reading as a real timestamp, and “the timestamp responsive to detecting the first frame” is reading as a first timestamp, [0049-0050], Formular 3, wherein the TS generator May determine the TX timestamp associated with the PTP packet based on the time Tref, ΔTX and Δ TX_SFD),
wherein the second multiframe is an Xth multiframe previous to the first multiframe in the channel, wherein X>0 (Fig.3, Fig. 5, illustrate reference frame, PHY Frame 206(N) and PHY Frame 404(0) is previous to the Ethernet Frame), and wherein the first timestamp indicates a time when a second location of the second multiframe arrives at a physical layer (Fig. 1, [0028-0029], disclose both TX timestamps and RX timestamps can be captured in the PHY, a PHY transceiver may generate an RX timestamp for a PTP packet based on a time at which a physical medium attachment PMA sublayer outputs, to a physical coding sublayer PCS, the PHY transceiver can adjust the RX timestamp to account for any offset or delay between the beginning of the PTP packet and the beginning of the one or more PHY frames. Fig. 4, Fig. 5, [0063-0065], Disclose the packet TS component may determine the offset K between the beginning of the PTP packet 406 and the beginning of the PTP
frame 404 based on the SFD information 407 received from the PTP packet processor
450 and frame synchronization signal 403 received from the RX PCS 440);
However, Chen does not explicitly teach when the data arrives at a channel forwarding layer; and implementing time synchronization between nodes and determining a round-trip delay of the packet between the nodes based on the real timestamp.
Yang, from the same or similar field of endeavor, teaches when the data arrives at a channel forwarding layer (Fig. 7A, [0059-0060], disclose after PTP message send to IP, Timestamp Unit TSU waiting for PTP necessary information from MAC and a timestamp
from a High Accuracy Timestamp Assist HATA, after that, TSU process the timestamp, Fig. 2, [0039], disclose HATA perform as “timestamp synchronization units” and provide a method of capturing the departure and arrival times of PTP messages on both transmit and receiver paths that includes the time traversing Physical Layers);
and implementing time synchronization between nodes (Abstract, “The master and slave node processors perform compensation of the node clock time by making adjustments to the node clock time for known time latency. The master and slave node timestamp synchronization units then output the node clock time as timestamps to corresponding timestamp units”) and determining a round-trip delay of the packet between the nodes based on the real timestamp (Fig. 2, [0041], disclose The HATA device 271
captures the arrival time of the scrambled SFD bit pattern at the SerDes interface of the Physical Layer 112 and generates a timestamp corresponding to the captured arrival time and transmit timestamp to the TSU 165 to further clock synchronization between a master side and a slave side of the communication device, Fig. 2, Fig.3, Fig.5, element 528, Fig. 6, [0050], capturing a clock time at which the start frame delimiter is identified, performing compensation of the clock time by making adjustments to the clock time for time latency, and time latency is the sum of bit offsets of the serializer/deserializer 349, 549 combined with latency caused by traversing the timestamp synchronization unit 221, wherein time latency is reading as a round-trip delay. Fig. 8, element 806, 808, 810,812, [0063-0065], disclose generic methods of using a time protocol decoder of a
timestamp synchronization unit to detect a time protocol message being transmitted on a transmission medium, performing compensation of the clock time by making adjustments to the clock time for time latency, and time latency is the sum of bit offsets of the serializer/deserializer combined with latency caused by traversing the synchronization unit. Fig. 5, Fig. 6, [0045-0046], disclose the data packets received by the SerDes interface are written to a FIFO memory 530, the SFD Pattern Detector 528 is used to detect the start position of the SFD from every FIFO entry, once the SFD is detected, a FIFO Compensation Unit calculating how many clock cycles are required for the SFD to traverse the SerDes Interface 549 to the Ethernet protocol block in RX side.).
Chen and Yang are both considered to be analogous to the claimed invention because they are in the same field of wireless communication. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the system of Chen and the features of determining a round-trip delay of the packet between the nodes based on the real timestamp as taught by Yang, for the benefit for supporting accurate timestamp indication, which allowing to detect round trip delay as low as just one sample delay (paragraph [0062]).
Claim 7 is analyzed and rejected according to Claim 1, Chen further teaches a memory (Fig. 6, element 630, Fig.7, element 730), configured to store instructions ([0077-0080], [0084-0087], disclose memory store one or more software modules, each software module includes instructions), and one or more processors (Fig. 6, element 620, Fig. 7, element 720) coupled to the memory and configured to execute the instructions ([0080, 0087], disclose each software module includes instructions that, when executed by the processing system, causes the timing synchronization controller to perform the corresponding functions).
Claim 18 is analyzed and rejected according to Claim 1, Chen further teaches A computer program product comprising computer-executable instructions that are stored on a non-transitory computer-readable medium ([0077-0080], [0084-0087], disclose memory store one or more software modules, each software module includes instructions, [0080, 0087], disclose each software module includes instructions that, when executed by the processing system, causes the timing synchronization controller to perform the corresponding functions).
Claim 2: Chen teaches the method of claim 1, wherein the first location comprises: a next bit of a start-of-frame delimiter (SFD) of the packet (Fig. 3, illustrate Ethernet Frame is after SFD).
Claim 8 is analyzed and rejected according to Claim 7 and Claim 2.
Claim 3: The combination of Chen and Yang teaches The method of claim 1, wherein the second multiframe comprises basic frames arranged based on slots, and wherein the second location comprises: a next bit of a start-of-frame delimiter (SFD) of a first basic frame of the second multiframe (Chen, [0091], the SFD is carried in a second frame following the first frame. the delay between the first frame and the packet may be determined based on a number of frames output by the PCS between the first frame and the second frame, the determining of the delay between the first frame and the packet may include determining an offset between the SFD of the packet and the beginning of the second
frame, [0043], “The SFD is an 8-bit pattern”. [0046], “the TX PCS 230 may output a respective frame synchronization signal 203 to the PTP timer 270 to signal the start of each PHY frame … the PTP packet processor 220 also may output a respective frame
synchronization signal 207 to the TS generator 280 to signal the start of a PHY frame in which the PTP packet 204 is to be encoded … when the frame synchronization signals 203 and 207 are aligned, the timing information 205 indicates a timing of a PHY
frame 206 that is N frames ahead of the PTP packet 204”.
Yang, [0041], “the high accuracy timestamp assist HATA device 271 continuously searches for a scrambled Start Frame Delimiter SFD bit pattern arriving from the transmission medium”).
Claim 9 is analyzed and rejected according to Claim 7 and Claim 3.
Claim 4: Chen teaches the method of claim 1, wherein determining the real timestamp comprises determining the real timestamp based on an interval between the second multiframe and the first multiframe (Fig. 3, [0056-0058], start location of Ethernet frame 306 is reading as first location, which can be calculated by combining Tref , ΔTX and Δ TX_SFD, Wherein ΔTX and/or Δ TX_SFD is the time interval between PHY Frame 0 and PHY Frame N, [0049], the TS generator 280 may determine the timestamp 201 TX timestamp associated with the PTP packet 204 based on the time Tref at which the TX PCS 230 outputs the reference frame to the TX PMA sublayer 240).
Claim 10 is analyzed and rejected according to Claim 7 and Claim 4.
Claim 5: Chen teaches the method of claim 1, wherein determining the real timestamp comprises determining the first timestamp as the real timestamp (Fig. 9, element 910, 920, [0028], disclose both TX timestamps and RX timestamps can be captured in the physical layer PHY).
Claim 11 is analyzed and rejected according to Claim 7 and Claim 5.
Claim 13: Chen teaches the method of claim 1, wherein the first location comprises a first bit of a start-of- frame delimiter (SFD) of the packet (Fig. 2, Fig. 3, element 304, [0063], each PTP packet 406 is an Ethernet packet having a preamble and an SFD followed by an Ethernet frame.).
Claim 14: Chen teaches the method of claim 1, wherein the first location comprises a first bit of a preamble code block of the packet (Fig. 2, Fig. 3, element 302, [0063], each PTP packet 406 is an Ethernet packet having a preamble and an SFD followed by an Ethernet frame, [0043], The preamble is a 56-bit pattern that can be used by a receiving device to synchronize its receiver clocks with the transmission of the TX packet).
Claim 15: Chen teaches the method of claim 1, wherein the second multiframe comprises basic frames arranged based on slots (Fig. 3, Fig.5, illustrate reference frame, PHY Frames and PTPT frames are located on different time slot, each PHY frame is reading as one basic frame),
and wherein the second location comprises a first bit of a start-of-frame delimiter (SFD) of a first basic frame of the second multiframe ([0091], the SFD is carried in a second frame following the first frame. the delay between the first frame and the packet may be determined based on a number of frames output by the PCS between the first frame and the second frame. In some implementations, the determining of the delay between the first frame and the packet may include determining an offset between the SFD of the packet and the beginning of the second frame).
Claim 16: Chen teaches the method of claim 1, wherein the second multiframe comprises basic frames arranged based on slots (Fig. 3, Fig.5, illustrate reference frame, PHY Frames and PTPT frames are located on different time slot, each PHY frame is reading as one basic frame),
and wherein the second location comprises a first bit of a preamble code block of a first basic frame of the second multiframe ([0062], Disclose each PHY Frame encoded with FEC coding scheme, FEC coding scheme may include Reed-Solomon codes and LDPC codes, descramble the bits of each FEC codeword and deserialize the scrambled bits prior to performing the decoding operation, wherein PHY Frame is reading as “basic frames”, and FEC coding scheme is reading as “code block”, “the bits of each FEC codeword” is reading as “a first bit of a preamble code block”).
Claim 19: Chen teaches the computer program product of claim 18, wherein the first location comprises at least one of a next bit of a start-of-frame delimiter (SFD) of the packet (alternative), a first bit of the SFD (Fig. 2, Fig. 3, element 304, [0063], each PTP packet 406 is an Ethernet packet having a preamble and an SFD followed by an Ethernet frame.), or a first bit of a preamble code block of the packet ([0043], The preamble is a 56-bit pattern that can be used by a receiving device to synchronize its receiver clocks with the transmission of the TX packet).
Claim 20: Chen teaches The computer program product of claim 18, wherein the second multiframe comprises basic frames arranged based on slots (Fig. 3, Fig.5, illustrate reference frame, PHY Frames and PTPT frames are located on different time slot, each PHY frame is reading as one basic frame), and wherein the second location comprises at least one of a next bit of a start-of-frame delimiter (SFD) of a first basic frame of the second multiframe (alternative), a first bit of the SFD ([0091], the SFD is carried in a second frame following the first frame. the delay between the first frame and the packet may be determined based on a number of frames output by the PCS between the first frame and the second frame. In some implementations, the determining of the delay between the first frame and the packet may include determining an offset between the SFD of the packet and the beginning of the second frame), or a first bit of a preamble code block of the first basic frame (alternative).
Claims 6, 12,17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20240223296 A1, hereinafter Chen) in view of Yang et al. (US 20180191802 A1, hereinafter Yang), and further in view of Sela et al. (US 20210392065 A1, hereinafter Sela).
Claim 6: Chen teaches the method of claim 1, Further comprising: determining the time as a moment at which the second location arrives at the physical layer (Fig. 3, element frame Sync 203, Frame Sync 207, [0049], formular 3, the TS generator 280 may determine the timestamp 201 /TX timestamp associated with the PTP packet 204 based on the time Tref at which the TX PCS 230 outputs the reference frame to the TX PMA sublayer 240, Fig. 9, element 910, 920, [0095], The timing synchronization controller detects a first frame of one or more frames output by a PMA sublayer of the communication device to a PCS of the communication device, generating a timestamp responsive to detecting the first frame);
However, Chen does not explicitly teach storing the first timestamp in a storage space as a second timestamp.
Sela, from the same or similar field of endeavor, teaches storing the first timestamp in a storage space as a second timestamp ([0054], “the computed timestamp may only include the least significant bits (LSBs) of time associated with the entry of the SFD into the pipeline. The most significant bits (MSBs) of the time associated with the entry of the SFD into the pipeline may be stored elsewhere. At a later stage, the computed
timestamp may be expanded using the stored value.”).
Chen and Sela are both considered to be analogous to the claimed invention because they are in the same field of wireless communication. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the system of Chen and the features of storing timestamp in a storage space as taught by Sela, for the benefit of allowing to add the timestamp to the packet associated with the identified
SFD after the packet is recognized after the PHY layer in the network device, so that each
packet is accurately timestamped (paragraph [0053]).
Claim 12: Chen teaches the apparatus of claim 7, wherein the ore or more processors are further configured to execute the instruction to cause the apparatus to: determining the time as a moment at which the second location arrives at the physical layer (Fig. 3, element frame Sync 203, Frame Sync 207, [0049], formular 3, the TS generator 280 may determine the timestamp 201 /TX timestamp associated with the PTP packet 204 based on the time Tref at which the TX PCS 230 outputs the reference frame to the TX PMA sublayer 240, Fig. 9, element 910, 920, [0095], The timing synchronization controller detects a first frame of one or more frames output by a PMA sublayer of the communication device to a PCS of the communication device, generating a timestamp responsive to detecting the first frame).
However, Chen does not explicitly teach storing the first timestamp in a storage space as a second timestamp; obtaining the second timestamp from the storage space; and determining the real timestamp based on the second timestamp.
Sela, from the same or similar field of endeavor, teaches storing the first timestamp in a storage space as a second timestamp ([0054], “the computed timestamp may only include the least significant bits (LSBs) of time associated with the entry of the SFD into the pipeline. The most significant bits (MSBs) of the time associated with the entry of the SFD into the pipeline may be stored elsewhere.”);
obtaining the second timestamp from the storage space ([0054], “the computed timestamp may only include the least significant bits (LSBs) of time associated with the entry of the SFD into the pipeline. The most significant bits (MSBs) of the time associated with the entry of the SFD into the pipeline may be stored elsewhere. At a later stage, the computed timestamp may be expanded using the stored value.”);
and determining the real timestamp based on the second timestamp ([0053], “The timestamp may then be added to the packet associated with the identified SFD after the packet is recognized after the PHY layer in the network device. … the timestamp is added to each SFD, … when PTP packets are identified at a later stage in the processing, each PTP packet has an accurate timestamp”).
The motivation for combining Chen and Sela regarding to the claim 6 is also applied to claim 12.
Claim 17: The combination of Chen and Yang does not explicitly teach the method of claim 6, wherein determining the real timestamp comprises: obtaining the second timestamp from the storage space; and determining the real timestamp based on the second timestamp.
Sela, from the same or similar field of endeavor, teaches obtaining the second timestamp from the storage space ([0054], “the computed timestamp may only include the least significant bits (LSBs) of time associated with the entry of the SFD into the pipeline. The most significant bits (MSBs) of the time associated with the entry of the SFD into the pipeline may be stored elsewhere. At a later stage, the computed timestamp may be expanded using the stored value.”);
and determining the real timestamp based on the second timestamp ([0053], “The timestamp may then be added to the packet associated with the identified SFD after the packet is recognized after the PHY layer in the network device. … the timestamp is added to each SFD, … when PTP packets are identified at a later stage in the processing, each PTP packet has an accurate timestamp”).
The motivation for combining Chen and Sela regarding to the claim 6 is also applied to claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form. The closest prior art reference is Kuchler et al. (US 20180288730 A1, hereinafter Kuchler), which describes a system for providing a verified range estimate in accordance with one or more of the time stamps of the verified received-data-packet.
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/Y.Z./Examiner, Art Unit 2472
/ANH VU H LY/ Primary Examiner, Art Unit 2472
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