Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is a response to an application filed on 03/31/2026 in which claims 1-10, 16-23, 25 and 28 are pending and ready for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN204392076U (hereinafter CN076) in view of CN103825505A (hereinafter CN505).
As to claims 1 and 16, CN076 discloses a power inverter (see Fig 1), comprising:
a first leg (Fig 1, 1) configured to output a first alternating voltage having a first phase;
a second leg (Fig 1, 2) configured to output a second alternating voltage having a second phase different from the first phase (three-phase inverter are different from each other because they are offset in time by 120 degrees) and
a third leg (Fig 1, 3) configured to output a third alternating voltage having a third phase different from the first phase and the second phase (three-phase inverter are different from each other because they are offset in time by 120 degrees), wherein the first leg comprises:
a first power metal oxide semiconductor field effect transistor (MOSFET) (Fig 1, T1) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of the first phase;
a second power MOSFET (Fig 1, T2) on the SiC substrate, and connected between the output terminal and a ground terminal; and
a first redundancy circuit comprising a first redundancy power transistor (Fig 1, T7, T8) configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing (see Figs 1 & 3, parags [0026-0027]); and
wherein the second leg (Fig 1, 2) comprises:
a third power MOSFET (Fig 1, T3) connected between the power terminal and a second output terminal configured to output a voltage of the second phase;
a fourth power MOSFET (Fig 1, T4) connected between the second output terminal and the ground terminal; and
CN076 does not disclose:
a second redundancy circuit comprising a second redundancy power transistor configured to replace the third power MOSFET based on the third power MOSFET failing and replace the fourth power MOSFET based on the fourth power MOSFET failing.
However, CN505 discloses a second redundancy circuit comprising a second redundancy power transistor configured to replace the third power MOSFET based on the third power MOSFET failing and replace the fourth power MOSFET based on the fourth power MOSFET failing (see Fig 1, parags [0012-0015]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the inverter of CN076 to include the second redundancy circuit as taught by CN505 in order to maintain the operation of the inverter.
As to claim 9, CN076 discloses the power inverter of claim 1, wherein the first redundancy circuit is configured to activate upon confirmation of failure while an inverter operates (CN076, see parags [0026-0027]).
Claim(s) 2-3 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN204392076U (hereinafter CN076) in view of CN103825505A (hereinafter CN505) further in view of Azumo et al (hereinafter Azumo) (US 2014/0094027 A1).
As to claims 2 and 17, the combination of CN076 and CN505 discloses the power inverter of claim 1, further comprising a first power module comprising the first leg (Fig 1, 1), a second power module comprising the second leg (Fig 1, 2), and a third power module comprising the third leg (Fig 1, 3).
The combination of CN076 and CN505 does not disclose wherein each of the first power module, the second power module and the third power module is provided on the SiC substrate.
However, Azumo discloses each of the first power module, the second power module and the third power module is provided on the SiC substrate (see Fig 2, parag [0045]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the inverter of CN076 and CN505 to include the teachings as taught by Azumo in order to achieve better performance for the inverter.
As to claims 3 and 18, the combination of CN076, CN505 and Azumo discloses the power inverter of claim 1, wherein the first redundancy power transistor comprises a redundancy MOSFET on the SiC substrate (Azumo, see Fig 2, parag [0045]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN204392076U (hereinafter CN076) in view of CN103825505A (hereinafter CN505) further in view of Signhal et al (hereinafter Signhal) (US 2025/0096836 A1).
As to claim 10, the combination of CN076 and CN505 discloses the power inverter of claim 1, wherein the first redundancy circuit is configured to activate based on failure information of a failed power transistor (see parags [0026-0027]).
The combination of CN076 and CN505 does not discloses a failed power transistor during a wafer testing operation.
However, Signhal discloses activating based on failure information of a failed transistor during wafer testing operation (see parag [0051]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the inverter of CN076 and CN505 to include the teachings as taught by Signhal in order to save power for the system.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (hereinafter Wu) (US 2024/0146227 A1) in view of CN103825505A (hereinafter CN505).
As to claim 21, Wu discloses an electronic control system for a vehicle (see Fig 1), the electronic control system comprising:
a battery (Fig 1, 114) configured to provide a direct current voltage;
a charging circuit (Fig 1, 124) configured to charge the battery using an external power source (Fig 1, 126); and
a motor driver (Fig 1, 104) configured to change the direct current voltage to a three-phase alternating voltage and to drive a motor using the three-phase alternating voltage, wherein the motor driver comprises at least one power inverter (Fig 2, 220), and wherein the at least one power inverter comprises:
a first power transistor (Fig 1, 216).
and a second power transistor (Fig 1, 218) connected in series between a power terminal and a ground terminal to form a first leg configured to output a first phase of the three-phase alternating voltage;
a third power transistor (Fig 1, 216) and a fourth power transistor (Fig 1, 218) connected in series between the power terminal and the ground terminal to form a second leg (Fig 1, second leg of the inverter 220) configured to output a second phase of the three-phase alternating voltage.
Wu does not discloses: at least one a first redundancy power transistor configured to replace a first failed power transistor of the at least one power transistor among the first power transistor and the second power transistor, based on the first failed power transistor being identified; and a second redundancy power transistor configured to replace a second failed power transistor among the third power transistor and the fourth power transistor, based on the second failed power transistor being identified.
However, CN505 discloses at least one a first redundancy power transistor (Fig 1, Q7) configured to replace a first failed power transistor of the at least one power transistor among the first power transistor (Fig 1, Q1) and the second power transistor (Fig 1, Q4), based on the first failed power transistor being identified; and a second redundancy power transistor (Fig 1, Q8) configured to replace a second failed power transistor among the third power transistor (Fig 1, Q3) and the fourth power transistor (Fig 1, Q6), based on the second failed power transistor being identified (see Fig 1, parags [0012-0015]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the system of Wu to include the teachings as taught by CN505 in order to effectively control the operation of the inverter.
As to claim 22, the combination of Wu and CN505 discloses the electronic control system for a vehicle of claim 21, wherein each of the first power transistor and the first redundancy power transistor comprises a SiCmetal oxide silicon field effect transistor (MOSFET) (Wu, see Fig 2, switches of the inverter 220), a SiC super junction structure transistor, a SiC double trench structure transistor, or an insulated gate bipolar transistor (SiC IGBT).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (hereinafter Wu) (US 2024/0146227 A1) in view of CN103825505A (hereinafter CN505) further in view of Stancu et al (hereinafter Stancu) (US 7,100,717 B2).
As to claim 23, the combination of Wu and CN0505 does not disclose the electronic control system for a vehicle of claim 21, wherein the at least one power inverter comprises: a first inverter; and a second inverter.
However, Stancu discloses wherein the at least one power inverter comprises: a first inverter (Fig 1, 130); and a second inverter (Fig 1, 150). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the system of Wu and CN505 to include the teachings as taught by Stancu in order to effectively control the power provided to the system.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (hereinafter Wu) (US 2024/0146227 A1) in view of CN103825505A (hereinafter CN505) further in view of Azumo et al (hereinafter Azumo) (US 2014/0094027 A1).
As to claim 25, the combination of Wu and CN505 discloses the electronic control system for a vehicle of claim 21, wherein the motor driver further comprises a gate driving circuit (CN505, see parags [0012-0015]) configured to control the at least one power inverter.
The combination of Wu and CN505 does not disclose wherein the gate driving circuit and the at least one power inverter are implemented on a SiC substrate.
However, Azumo discloses wherein the gate driving circuit and the at least one power inverter are implemented on a SiC substrate (see Fig 2, parag [0045]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the inverter of Wu and CN505 to include the teachings as taught by Azumo in order to achieve better performance for the inverter.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (hereinafter Wu) (US 2024/0146227 A1) in view of CN103825505A (hereinafter CN505) further in view of Signhal et al (hereinafter Signhal) (US 2025/0096836 A1).
As to claim 28, the combination of Wu and CN505 discloses the electronic control system for a vehicle of claim 21, wherein the motor driver further comprises a gate driving circuit (CN505, see parags [0012-0015]) configured to control whether to use the first redundancy power transistor or the second redundancy power transistor.
The combination of Wu and CN076 does not disclose whether to use the first redundancy power transistor or the second redundancy power transistor based on failure information of a wafer.
However, Signhal discloses whether to use the first redundancy power transistor or the second redundancy power transistor based on failure information of a wafer.
. (see parag [0051]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the inverter of Wu and CN505 to include the teachings as taught by Signhal in order to save power for the system.
Allowable Subject Matter
Claims 4-8, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the cited prior arts alone or in combination fail to disclose:
“a controller configured to control a fuse-cell coding block to replace a failed MOSFET
with the redundancy MOSFET”.
As to claim 19, the cited prior arts alone or in combination fail to disclose:
“the controller is further configured to control a failed power transistor to be replaced using the first redundancy power transistor or the second redundancy power transistor by controlling a fuse-cell coding block”.
Response to Arguments
Applicant’s arguments, see pages 10-15, filed on 03/31/2026, with respect to the rejection(s) of claim(s) claims 1, 16 and 21 under 102(a)(1) and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CN076, CN505 and Wu et al, Azumo et al, Signhal et al, Stancu et al.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUC M PHAM whose telephone number is (571)272-5026. The examiner can normally be reached 10:00 am - 6:00 pm, Monday to Friday.
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/DUC M PHAM/Examiner, Art Unit 2836 August 19, 2026
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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