DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 05/21/2026. Claims 2, 7-8, 10 and 14 have been amended. Claims 18-20 are new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US 20100180083 A1] in view of Garcia [US 2019/0079874 A1].
Claim 1 is rejected over Lee and Garcia.
Lee teaches “An apparatus comprising: a non-volatile memory comprising a plurality of non-volatile memory code blocks, respective non-volatile memory code blocks containing a plurality of instructions to be executed by a processor;” as “Such a system 48 could include a non-volatile memory 52 (e.g., disk, EPROM, EEPROM, flash memory, ROM, etc.), a bus 54 for allowing communication between components of the system 48,” [¶0027]
“a volatile cache memory comprising a plurality of cache code blocks, respective cache code blocks to receive one of the plurality of non-volatile memory code blocks, the volatile cache memory to provide an instruction based at least on a cache address;” as “a random-access (main) memory 44 (e.g., dynamic RAM (DRAM))” [¶0027]
“an instruction decoder to receive an instruction address, the instruction address comprising a first portion and a second portion;” as “FIGS. 5A-5F are schematic diagrams showing hardware implementations of the decoder circuit of the cache memory of the present invention,” [¶0020]
“a content addressable memory (CAM) comprising:” as “It is noted that another way to implement the decoder circuit 20 is by using a content-addressable memory (CAM), such that the LNregs 22 are implemented as a CAM array.” [¶0044]
“a storage array comprising a plurality of data words, respective data words comprising a valid tag and an index, respective data words corresponding to respective cache code blocks of the plurality of cache code blocks;” as “the context RMT_ID is known shortly after the Instruction Fetch stage, and an index miss can be detected before even the tag is read out of the tag array 24.” [¶0052]
“a comparison circuit, the comparison circuit to compare the first portion of the received instruction address and the respective indices of the plurality of data words in the storage array, and the comparison circuit to generate a volatile cache code block address based on the valid tag and a result of the comparison;” as “The cache memory 10 also includes a tag comparator circuit which includes a comparator 26 and AND gate 28, for determining whether the selected tag element 25 in the tag array 24 matches the tag bits 14.” [¶0031]
Lee does not explicitly teach a concatenation circuit to concatenate the volatile cache code block address and the second portion of the received instruction address to generate the cache address; and
a block invalidation circuit coupled to the volatile cache memory, the block invalidation circuit to, based on receiving a write transaction to a valid cache code block of the plurality of cache code blocks, update at least one valid tag in the storage array of the CAM, the at least one valid tag corresponding to the valid cache code block of the plurality of cache code blocks, and to update at least one cache code block in the volatile cache memory.
However, Garcia teaches “a concatenation circuit to concatenate the volatile cache code block address and the second portion of the received instruction address to generate the cache address; and” as “the shareable tag portion may be combined, or concatenated, with the individual tag portion associated with the cache line to correspond with (at least part of) a storage identifier, for example a storage address, corresponding to a storage location in the data storage.” [¶0080]
“a block invalidation circuit coupled to the volatile cache memory, the block invalidation circuit to, based on receiving a write transaction to a valid cache code block of the plurality of cache code blocks, update at least one valid tag in the storage array of the CAM, the at least one valid tag corresponding to the valid cache code block of the plurality of cache code blocks, and to update at least one cache code block in the volatile cache memory.” as “A cache line in the valid state 330 may transition back to the invalid state 300, for example if the cache line is invalidated, or evicted, as previously described.” [¶0119]
Lee and Garcia are analogous arts because they teach storage system and cache memory addressing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Garcia before him/her, to modify the teachings of Lee to include the teachings of Garcia with the motivation of allowing a shareable tag storage location to be re-used, but may selectively prevent instructions from accessing the shareable tag storage location after re-use. For example, new instructions may not be allowed to access the re-used shareable tag storage location when trying to access any individual tag portion (and associated cache line) that pointed to the shareable tag storage location before it was re-used. [Garcia, ¶0066]
Claim 2 is rejected over Lee and Garcia.
Lee teaches “the comparison circuit to generate the volatile cache code block address based on the first portion of the received instruction address numerically matching a respective index within the storage array and based on a valid tag in a valid state, the valid tag corresponding to the numerically matching respective index.” as “If a line number register with a matching value for the index bits and context identifier exists, a corresponding tag element from the cache tag memory is accessed and compared to the tag bits also in the address provided to the cache memory.” [¶0014]
Claim 3 is rejected over Lee and Garcia.
Lee teaches “the comparison circuit to generate the volatile cache code block address based on a memory access in the CAM.” as “The address decoder 20 generates an output 34 which indicates whether an index hit or index miss has occurred, i.e., whether a matching index exists in the LNregs 22 which matches the index bits 16 and the context RMT_ID 18. ” [¶0030]
Claim 4 is rejected over Lee and Garcia.
Lee teaches “the block invalidation circuit to set the at least one valid tag in the storage array of the CAM to a valid state, and to write at least one index to the storage array.” as “The flag bit "V" 29 indicates if the corresponding tag value is valid, i.e., whether the tag element 25 contains a valid tag value.” [¶0031]
Claim 5 is rejected over Lee and Garcia.
Lee does not explicitly teach the block invalidation circuit to set the at least one valid tag to an invalid state, and to write at least one data word to the volatile cache memory.
However, Garcia teaches “the block invalidation circuit to set the at least one valid tag to an invalid state, and to write at least one data word to the volatile cache memory.” as “A cache line in the valid state 330 may transition back to the invalid state 300, for example if the cache line is invalidated, or evicted, as previously described. Alternatively the cache line may be reallocated and transition directly to the allocated state 310. ” [¶0119]
Claim 6 is a system claim rejected over Lee and Garcia under the same rationale of rejection of claim 1.
Claim 7 is a system claim rejected over Lee and Garcia under the same rationale of rejection of claim 2.
Claim 8 is a system claim rejected over Lee and Garcia under the same rationale of rejection of claim 4.
Claim 9 is rejected over Lee and Garcia.
Lee does not explicitly teach the block invalidation circuit to write a first index value to one of the plurality of data words of the storage array based on the first index value not in the plurality of data words of the storage array.
However, Garcia teaches “the block invalidation circuit to write a first index value to one of the plurality of data words of the storage array based on the first index value not in the plurality of data words of the storage array.” as “A cache line in the valid state 330 may transition back to the invalid state 300, for example if the cache line is invalidated, or evicted” [¶0119]
Claim 10 is a system claim rejected over Lee and Garcia under the same rationale of rejection of claim 5.
Claim 11 is rejected over Lee and Garcia.
Lee does not explicitly teach the block invalidation circuit to write at least one data word to the volatile cache memory based on a first index value matching an index in the storage array of the CAM.
However, Garcia teaches “the block invalidation circuit to write at least one data word to the volatile cache memory based on a first index value matching an index in the storage array of the CAM.” as “A cache line in the valid state 330 may transition back to the invalid state 300, for example if the cache line is invalidated, or evicted” [¶0119]
Claim 12 is rejected over Lee and Garcia.
Lee does not explicitly teach the block invalidation circuit to invalidate at least one entry in the volatile cache memory during a reset state.
However, Garcia teaches “the block invalidation circuit to invalidate at least one entry in the volatile cache memory during a reset state.” as “The STD of FIG. 3 also shows a reset transition to the invalid state 300. This transition may correspond to a reset instruction to reset, or restart, the system.” [¶0125]
Claim 13 is a method claim rejected over Lee and Garcia under the same rationale of rejection of claim 1.
Claim 14 is a method claim rejected over Lee and Garcia under the same rationale of rejection of claim 2.
Claim 15 is a method claim rejected over Lee and Garcia under the same rationale of rejection of claim 3.
Claim 16 is rejected over Lee and Garcia.
Lee teaches “the writing the updated index and the updated valid tag to the content addressable memory and writing at least one data word to the cache memory comprising writing the updated index and the updated valid tag representing a valid index based on the updated index not matching an index in the content addressable memory.” as “The LNregs are updated when cache line replacements occur, and a new line's context RMT_ID and index bits are written to the RMT_ID field and line_num field of a selected LNreg, respectively.” [¶0039]
Claim 17 is rejected over Lee and Garcia.
Lee teaches “the writing the updated index and the updated valid tag to the content addressable memory and writing at least one data word to the cache memory comprising writing the updated index and the updated valid tag representing an invalid index based on the updated index matching an index in the content addressable memory.” as “evict(R) Write back R if it is dirty; invalidate R (i.e., set V-bit in tag element to "0").” [Table 2]
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US 20100180083 A1] in view of Garcia [US 2019/0079874 A1] and in further view of Jenne et al. [US 2018/0032439 A1].
Claim 18 is rejected over Lee, Garcia and Jenne.
The combination of Lee and Garcia does not explicitly teach the block invalidation circuit to invalidate at least one entry in the volatile cache memory during a reset state.
However, Jenne teaches “the block invalidation circuit to invalidate at least one entry in the volatile cache memory during a reset state.” as “In method 300 (at 332) the cache is reset (e.g., by executing an instruction to perform a write-back operation at all internal and external caches and invalidate the caches,” [¶0072]
Lee, Garcia and Jenne are analogous arts because they teach storage system and cache memory addressing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee, Garcia and Jenne before him/her, to modify the teachings of combination of Lee and Garcia to include the teachings of Jenne with the motivation of CPU caches configured for write-back provide performance advantages over write-through caches. For example, in systems that access persistent memory via the SRAM memory interface of the CPU, a write-back cache is desirable for performance reasons. [Jenna, ¶0003]
Claim 20 is rejected over Lee, Garcia and Jenne.
The combination of Lee and Garcia does not explicitly teach the block invalidation circuit to write a first index value to one of the plurality of data words of the storage array based on the first index value not in the plurality of data words of the storage array.
However, Jenne teaches “the block invalidation circuit to write a first index value to one of the plurality of data words of the storage array based on the first index value not in the plurality of data words of the storage array.” as “method 300 continues at label C. In method 300, if (at 316) it is determined that the state of the cache line identified by the current index and way [cl(index, way)] is not in the modified state, method 300 continues at 324. In method 300, if (at 316) the state of the cache line identified by the current index and way [cl(index, way)] is modified, then (at 318) the cache line identified by cl(index, way) is flushed.” [¶0070]
Lee, Garcia and Jenne are analogous arts because they teach storage system and cache memory addressing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee, Garcia and Jenne before him/her, to modify the teachings of combination of Lee and Garcia to include the teachings of Jenne with the motivation of CPU caches configured for write-back provide performance advantages over write-through caches. For example, in systems that access persistent memory via the SRAM memory interface of the CPU, a write-back cache is desirable for performance reasons. [Jenna, ¶0003]
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US 20100180083 A1] in view of Garcia [US 2019/0079874 A1] and in further view of Baronne [US 2024/0070088 A1].
Claim 19 is rejected over Lee, Garcia and Baronne.
The combination of Lee and Garcia does not explicitly teach the comparison circuit to generate the volatile cache code block address based on a memory access in the CAM.
However, Baronne teaches “the comparison circuit to generate the volatile cache code block address based on a memory access in the CAM.” as “Then at stage 1112, a memory request is generated to read the contents of a memory address into data cache.” [¶0165]
Lee, Garcia and Baronne are analogous arts because they teach storage system and cache memory addressing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee, Garcia and Baronne before him/her, to modify the teachings of combination of Lee and Garcia to include the teachings of Baronne with the motivation of reducing the latency for instructions that need to issue multiple commands to a processor's data cache, such as during a multi-line eviction. [Baronne, ¶0029]
Response to Arguments
Applicant's arguments filed on 05/21/2026 have been fully considered but they are not persuasive.
Regarding Claim 1, applicant argues that the combination of Lee and Garcia Guirado fails to teach or suggest the limitation requiring the block invalidation circuit, “based on receiving a write transaction to a valid cache code block,” to update at least one valid tag in the storage array of the CAM and to update at least one cache code block in the volatile cache memory. In particular, Applicant contends that Garcia's invalidation or eviction is based on “usage indicators,” rather than on receipt of a write transaction to a valid cache code block.
Examiner respectfully disagrees. Garcia's disclosure of usage indicators in isolation from Garcia's overall disclosure concerning the processing of storage access instructions and the resulting transitions of cache lines between cache-line states.
Garcia describes a cache architecture in which cache lines have associated cache-line states and in which storage access instructions affect the status and use of the corresponding cache lines. Garcia further describes transitions between the valid and invalid states, including that a cache line in the valid state may subsequently transition back to the invalid state when the cache line is invalidated or evicted. See, e.g., Garcia ¶ [0115]-[0119]. Thus, Garcia's disclosure is not limited to a system in which invalidation occurs independently of cache transactions.
Applicant's reliance on Garcia ¶ [0090] does not establish otherwise. The disclosure that usage indicators may permit “inactive” cache lines to be evicted for allocation to a new request describes a mechanism for identifying or selecting a cache line that may be reused. It does not establish that the subsequent invalidation, updating, and reuse of that cache line are unrelated to the storage-access request that causes the cache location to be reallocated. Garcia's disclosure therefore should not be interpreted as requiring the usage indicator itself to constitute the transaction that updates the cache. Rather, the usage indicator identifies a cache line available for replacement, while the processing of a storage access request results in the corresponding cache-line state and contents being changed as necessary for reuse.
Moreover, the rejection is based on the combined teachings of Lee and Garcia, rather than on Garcia individually satisfying every limitation of claim 1. A reference relied upon in an obviousness combination need not individually disclose the complete claimed invention. The relevant inquiry is what the combined teachings would have suggested to one of ordinary skill in the art.
Accordingly, Applicant's argument that Garcia's use of a usage indicator precludes the claimed updating “based on receiving a write transaction” is not persuasive. The rejection of claim 1 under 35 U.S.C. § 103 is therefore maintained.
Regarding claim 3, applicant further argues that Lee fails to teach the claimed comparison circuit configured to “generate the volatile cache code block address based on a memory access in the CAM.” Applicant argues that Lee's output 34 merely represents a binary Index Hit/Index Miss indication and therefore cannot itself constitute the claimed volatile cache code block address.
Applicant's argument regarding output 34, considered by itself, is acknowledged; however, it does not address the entirety of Lee's address-decoding operation relied upon by the Examiner.
Lee does not merely generate an abstract hit/miss indication. Lee describes an address decoder 20 that receives address information and uses that information to select a corresponding location within the cache memory. In connection with Fig. 5A, Lee explains that the address-decoder circuitry selects a single word line 78 in memory cell array 80 when the decoding/matching operation produces the appropriate hit condition, whereas no word line is selected when an Index Miss occurs. Thus, although Index Hit/Miss output 34 indicates whether a hit or miss occurred, the associated address-decoder circuitry also identifies/selects the particular memory location corresponding to the memory access. Lee's address-decoder structure and operation therefore must be considered as a whole rather than limiting the disclosure to the binary value appearing at output 34. Lee's discussion of its cache-addressing architecture and address-decoder operation is provided, inter alia, in the portions describing Figs. 2 and 5A.
Stated differently, the Examiner does not interpret the single-bit Index Hit/Miss signal, standing alone, as numerically encoding the volatile cache code block address. Rather, the cited address-decoder/comparison circuitry receives the memory address, performs the comparison/decoding operation, and, upon the appropriate match, produces the selection of the particular cache-memory word line corresponding to that address. Under the broadest reasonable interpretation, such identification/selection of a particular cache location constitutes generation of information identifying the cache location, i.e., the claimed volatile cache code block address.
Applicant's argument focuses solely on the form of output 34 while disregarding the resulting location-selection operation performed by Lee's decoder circuitry. The claim does not require the generated “volatile cache code block address” to have any particular numerical format, bit width, or address encoding. Accordingly, Lee's disclosure of generating a location-specific word line selection from the supplied memory address reasonably teaches or suggests the claimed generation of a volatile cache code block address based on the memory access.
Therefore, Applicant's argument does not overcome the rejection of claim 3.
Applicant asserts that independent claims 6 and 13 are allowable for reasons analogous to those presented with respect to claims 1 and 3, and that the remaining dependent claims are allowable by virtue of their dependency.
These arguments are not persuasive for substantially the same reasons discussed above with respect to claims 1 and 3. Because Applicant has not identified additional limitations in claims 6 and 13, or in the dependent claims, that independently distinguish the claimed subject matter from the combined teachings of Lee and Garcia, the arguments do not overcome the rejection.
Accordingly, the rejection of claims 1–17 under 35 U.S.C. § 103 over Lee in view of Garcia Guirado is maintained. Newly added claims 18–20 were addressed according to their respective dependencies and any additional limitations recited therein.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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