Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over BLANER et al. (US Pub. 2019/0332549) in view of Feeley et al. (Pub. No.: US 2014/0108678).
Regarding independent claims 1 and 13, BLANER discloses a computational storage system comprising:
storage (Fig.1: system memory 106) configured to store data of a shared file system (Fig.1 and [0036]: memory access requests by processing units 102 and other coherence participants requesting coherent access to various memory blocks within various shared system memories 106 or cached within data processing system 100. Also coupled to system interconnect 110 is a nest memory management unit (NMMU) 112, which provides effective (virtual)-to-real address translation services to requesting device. Thus, BLANER teaches storage configured to store data that is shared among multiple processing units); and
accelerator logic (Fig.1: an accelerator unit 120) configured to perform a computational task using the stored data responsive to a command received from a host (Fig.1: processing unit 102) ([0038]: one or more of processing units 102 may be coupled by an accelerator interface 116 to an accelerator unit 120, as described further below. As utilized herein, the term "accelerator" is defined to refer to a computational device specifically configured to perform one or more computational, data flow, data storage, and/or functional tasks as compared with a general. Thus, BLANER teaches accelerator logic configured to perform computational tasks using data stored in shared system memory),
wherein the shared file system is accessible to the host and the computational storage system (Fig.1 & 2 and [0036]: Each of processing units 102 is coupled by a memory bus 104 to a respective one of shared system memories 106, the contents of which may generally be accessed by any of processing units 10, thereby disclosing host access to the stored data, [0045]: Host attach logic 240 may issue memory access requests and participate in coherency messaging on behalf of accelerator unit 120. Thus, BLANER teaches that the same stored data is accessible to both the host and the accelerator logic, corresponding to a shared file system as recited in claim 1).
However, BLANER does not specifically teach wherein the accelerator logic is configured to access the stored data using a pointer received from the host.
Feeley teaches wherein the accelerator logic is configured to access the stored data using a pointer received from the host ([0013]: setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. [0035]: a pointer can be included in the DID registers. The pointer can consist of the address in memory 316 where the data space is located. The address included in the pointer can point the DID registers containing device class independent information to the device class dependent information in memory 316).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a pointer identifying a location of data, as taught by Feeley into the data processing system of BLANER, in order to enable the computational storage system to efficiently identify the specific data to be processed without requiring address translation.
Regarding claims 2 and 15, Feeley teaches wherein the accelerator logic is further configured to access the stored data using a data size associated with the pointer ([0035]: a pointer can be included in the DID registers. The pointer can consist of the address in memory 316 where the data space is located. The address included in the pointer can point the DID registers containing device class independent information to the device class dependent information in memory 316.).
Regarding claims 3 and 16, BLANER teaches wherein the accelerator logic is configured to perform the computational task based at least in part on configuration information or compiled instructions received from the host ([0053]: To support the configurability of an associated real address (RA)-based directory 600 of the contents of accelerator cache 302 that resides in host attach logic 240 (see, e.g., FIG. 6 described below), accelerator unit 120 preferably allocates internal or external storage for cache configuration parameters defining a desired configuration of RA-based directory 600. Although in some embodiments, these cache configuration parameters can be stored, for example, in software-defined storage locations (e.g., in system memory 106), in the depicted embodiment accelerator unit 120 is equipped with a set of hardware cache configuration registers 330 for storing the cache configuration parameters. In the illustrated example, cache configuration
registers 330 include at least a host tag number (HTN) register 332 for specifying a desired number of entries 320 to be utilized in host tag array 308).
Regarding claims 4 and 18, BLANER teaches wherein the shared file system is accessible by at least one other host (Fig.1: two processors).
Regarding claim 5, BLANER teaches wherein the accelerator logic includes an application-specific integrated circuit (ASIC) ([0038]: Accelerator units 120 can be implemented, for example, as an integrated circuit including programmable logic (e.g., programmable logic array (PLA) or field programmable gate array ( FPGA)) and/or custom integrated circuitry (e.g., application-specific integrated circuit ( ASIC))).
Regarding claim 6, BLANER teaches wherein the accelerator logic includes a field programmable gate array (FPGA) ([0038]: Accelerator units 120 can be implemented, for example, as an integrated circuit including programmable logic (e.g., programmable logic array (PLA) or field programmable gate array ( FPGA)) and/or custom integrated circuitry (e.g., application-specific integrated circuit ( ASIC))).
Regarding claims 7 and 19, BLANER teaches wherein the command includes at least one application program interface (API) call ([0041]: fixed- and floating-point arithmetic instructions, logical instructions, and memory access instructions that request read and/or write access to a memory block in the coherent address space of data processing system 100).
Regarding claims 8 and 17, BLANER teaches wherein the storage is configured to receive the data from a data collection device separate from the host at a location provided by the host (Fig.1 and [0036]: memory access requests by processing units 102 and other coherence participants requesting coherent access to various memory blocks within various shared system memories 106 or cached within data processing system 100).
Regarding claims 9 and 14, BLANER teaches wherein the storage is configured to store a result of the computational task (Fig.1 and [0038]: one or more of processing units 102 may be coupled by an accelerator interface 116 to an accelerator unit 120, as described further below. As utilized herein, the term “accelerator” is defined to refer to a computational device specifically configured to perform one or more computational, data flow, data storage, and/or functional tasks (as compared with a general-purpose CPU, which is designed to handle a wide variety of different computational tasks).
Regarding claims 10 and 20, BLANER teaches wherein the accelerator logic is configured to access other data directly from a different computational storage system via a data path that bypasses the host (Fig.1 and Fig.2).
Regarding claim 11, BLANER teaches host interface logic configured to provide direct memory access (DMA) to the host (Fig.1 and Fig.2).
Regarding claim 12, BLANER teaches a storage controller configured to communicate with the storage based on the command (Fig.1 & 2 and [0036]: Each of processing units 102 is coupled by a memory bus 104 to a respective one of shared system memories 106, the contents of which may generally be accessed by any of processing units 10, thereby disclosing host access to the stored data, [0045]: Host attach logic 240 may issue memory access requests and participate in coherency messaging on behalf of accelerator unit 120. Thus, BLANER teaches that the same stored data is accessible to both the host and the accelerator logic).
Response to Arguments
Applicant’s arguments filed on 05/04/2026 have been fully considered but they are not persuasive.
1st Point of Argument
Regarding Applicant’s remarks on pages 6-7, the applicants argue that Blaner teaches away from the accelerator unit 120 accessing stored data in the storage using a pointer received from the host. If a pointer is incorporated as suggested by the Examiner, such modification would remove the agnosticism discussed in Blaner and contradicts Blaner's principle of operation. Stated differently, even if Feeley teaches a pointer (a point which Applicant does not concede), one would not be motivated to modify Blaner's data processing system to incorporate such "pointer."
In response, Examiner disagrees.
The rejection does not rely on Feeley to eliminate or replace Blaner’s address translation mechanism, nor does it modify accelerator unit 120 to perform address translation. Rather Feeley is relied upon only for teaching a pointer provided by the host to identify data for processing by the accelerator. Using such a pointer does not require removing or changing Blaner’s existing address translation or host attach logic. Furthermore, Applicant has not identified any disclosure in Blaner that criticizes the use of a host-provided pointer for identifying data to be processed.
2nd Point of Argument
Regarding Applicant’s remarks on page 7, the applicants argue that if Blaner's translation step was skipped by incorporating a pointer, as suggested by the Examiner, the host attach logic 240 would need to be severely modified. Removing this translation step would require drastic modifications to the host attach logic 240, which would fundamentally change Blaner's data processing system 100. Such drastic modifications would render Blaner's data processing system inoperable for its intended purpose of coherent accelerator cache management. Therefore, the suggested modification cannot support an obviousness rejection.
In response, Examiner disagrees.
Claim 1 only recites accessing stored data using ‘a pointer received from the host’. Claim 1 does not require the pointer to be a real address or require replacing Blaner’s address translation mechanism. Applicant’s arguments read limitations into the claim that are not recited.
Therefore, It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate using Feeley’s pointer based data identification technique into Blaner’s computational storage system as predictable use of known prior art elements for their intended purpose.
Therefore, the rejection under 35 USC § 103 is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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