DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 10/25/24; 2/4/25; 6/13/25 and 7/10/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5-11, 13-18 and 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Choi (US 2023/0139732).
As per claims 1 and 10, Choi teaches a system (Choi: par. [0006]; claims 1 and 20)/a method (Choi: claim 10)/a system comprising a memory pool (Choi: par. [0052]); one or more processors (par. [0074]) connected to the memory pool; and instructions that, when executed by the one or more processors, cause the one or more processors to comprising:
a first memory layer (Choi: fig. 2A; item 210; par. [0042]: “addressing scheme for a dimension-oriented (or “layer-oriented”) scale-up or scale-out clustering architecture”; par. [0054]) comprising:
a first memory node of a memory pool (Choi: fig. 2A; items 205 or fig. 2A reproduced below with L1 layer 1, and N1 node 1), with node numbers 0, 1, 2, 3; fig. 9, item N2 is a first node) and a second memory node of the memory pool, the second memory node being connected to the first memory node by one link in the first memory layer (Choi: fig. 2A; items 205, with node numbers 0, 1, 2, 3; fig. 9, item N1 is the second node, par. [0054]: “creating a cluster 210 (which may be referred to as a “basic building block cluster”), which is a one-dimensional cluster. The connections or “links” that connect the nodes 205 together may be memory-centric connections”; par. [0042]: “The systems disclosed herein provide methods for abstraction on resource pools with a large number of memory or storage nodes”); and
a switch (Choi: par. [0065]: controller 705) configured to provide access to the first memory node from the second memory node based on (Choi: par. [0070]: “receiving, at 805, by a first node having an external port for making a connection to a host, a first request, addressed to a second node connected to the first node by a first memory-centric connection…forwarding, at 810, by the first node, the first request to the second node”; here it is noted that Choi teaches first node is providing an access to the second node; Choi: fig. 9, the first node N2 is being accesses via a second node N1 and according to current disclosure par. [0107]: first memory node can be any other memory node, which means the first or second can be interchangeable, therefore Choi teaches claimed first and second node as second and first nodes):
a first identifier corresponding to the first memory layer; and a second identifier corresponding to a location of the first memory node in the memory pool (Choi: par. [0046]: “The dimension information of the nodes and the port information of the links on the nodes may be part of the addressing scheme (discussed in further detail below). In some embodiments, (i) dimension information, (ii) node IDs in the given dimension”; par. [0071]. It is noted that the dimension information is layer identifier and the node ID provides location of the memory node). See Choi: fig. 2A below for designation of Layers and nodes. L1 is a first layer, N1 is first memory node, N2 is a second memory node and L2 is a second layer and N3 is a third memory node.
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As per claims 2, 11 and 18, Choi teaches wherein the first identifier is encoded in first bits of a message received by the switch, and the second identifier is encoded in second bits of the message received by the switch (Choi: fig. 1; par. [0047]: “For the node addressing scheme, the dimension and node ID information may be considered together... The dimension information is embedded in the 2-bit field of the node address space…the embodiment of FIG. 1, 32 bits are assigned for the node address space, only 20 bits are occupied for node IDs for 10 dimensions”).
As per claims 5, 13 and 20, Choi teaches wherein the second identifier corresponds to a port identifier associated with the first memory node (Choi: fig. 1, par. [0048]: “the dimension information and the port identifier (ID) information are considered together”; par. [0049]: “The routing port address space for each dimension consists of a 3-bit field”).
As per claims 6 and 14, Choi teaches the system of claim 1, further comprising a second memory layer comprising a third memory node of the memory pool, the third memory node being connected to the second memory node by one link from the second memory layer to the first memory layer (Choi: fig. 2A, items 220, 225, see fig. 2A reproduced above, where, L2 is a second memory layer comprising a third node N3, coupled to the second memory node N2 of first layer L1 and first memory node N1), wherein the switch is further configured to provide access to the first memory node from the third memory node based on: a third identifier corresponding to the second memory layer; the first identifier corresponding to the first memory layer; and the second identifier corresponding to a location of the first memory node in the memory pool (Choi: fig. 2A, items 205, 210 and 225 are equivalent to current disclosure fig. 2, where in fig. 2A of Choi, the top cluster is a second layer with node 0 (dotted) which is a third memory node and it is connected to the bottom clusters, including the first node N2 and the second Node N1 and as noted with respect to claim 1 above, Choi provides the dimension/layer ID bits, node ID bits and port IDs, based on which the nodes are accessed).
As per claims 7 and 15, Choi teaches wherein the third memory node is connected to the first memory node through the second memory node (Choi: fig. 2A, item 225 reproduced above, where N3 is connected to the N1 via N2).
As per claims 8 and 16, Choi teaches the system of claim 6, further comprising a third memory layer comprising a fourth memory node of the memory pool, the fourth memory node being connected to the third memory node by one link from the third memory layer to the second memory layer, wherein the switch is further configured to provide access to the first memory node from the fourth memory node based on: a fourth identifier corresponding to the third memory layer; the third identifier corresponding to the second memory layer; the first identifier corresponding to the first memory layer; and the second identifier corresponding to a location of the first memory node in the memory pool (See fig. 2D, items 220 and 250 provides topologies with different layers/dimensions and as explained with respect to claim 1 above, the addressing scheme comprise layer/dimension IDs, node IDs and port IDs for accessing particular node within the particular layer). Choi fig. 2D is reproduced below with L1 comprising a second memory node N2, coupled to the Node N1 in first layer, the third node N3 in second layer L2, which then is connected to the fourth memory node N3 in layer L3. The figure is applicable to claims 8 and 9.
As per claims 9 and 17, Choi teaches The system of claim 6, further comprising a third memory layer comprising a fourth memory node of the memory pool, the fourth memory node being connected to the third memory node by one link from the third memory layer to the second memory layer, wherein the fourth memory node is connected to the first memory node through the third memory node and the second memory node. See claims 1, 6, and 8 above.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2023/0139732) as applied to claims 2, 11 and 18 above, and further in view of Choi (US 10,057,334) (Choi-334 here in after).
As per claim 3, Choi fails to teach wherein the first bits and the second bits are encoded in a header field of the message. Choi-334 teaches wherein the first bits and the second bits are encoded in a header field of the message (Choi-334: fig. 2C; col. 10, lines 3-28). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a packet comprising a header with a node address entry and port address entry with the first bits and the second bits as taught by Choi-334 in the system of Choi to provide packet based messaging using header to provide efficiency, flexibility and reliability by transmitting the data in small/segmented packets with headers.
As per claim 4, Choi and Choi-334 teach wherein the first bits of the first identifier are encoded in at least one of source bits, destination bits, or port bits of the message, or in reserve bits of the message (Choi-334: fig. 2C; col. 10, lines 3-28: address entry indicating source node, destination node and routing port address and dimension).
Claims 12 and 19 are similar in scope with claim 4 above and thus rejected under same rationales as applied to claim 4 above.
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al. (US 2021/0241078) teaches a system for synching data in computing nodes connected in torus topology.
Henry et al. (US 2010/02465810 teaches an apparatus for routing packets in hyper-torus topology connected nodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138