Prosecution Insights
Last updated: October 27, 2026
Application No. 18/927,669

SECURELY MODIFYING ACCESS TO A DEBUG PORT

Non-Final OA §102§103
Filed
Oct 25, 2024
Priority
Aug 25, 2022 — continuation of 12/130,726
Examiner
SUN, SCOTT C
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
2 (Non-Final)
88%
Grant Probability
Favorable
2-3
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
595 granted / 676 resolved
+33.0% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
7 currently pending
Career history
683
Total Applications
across all art units

Statute-Specific Performance

§101
7.8%
-32.2% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
15.7%
-24.3% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 676 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 21 and 28 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mendes (pub # US 20210357311 A1). The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 1, Mendes discloses memory device (memory system shown in figure 2) comprising: a debug register (slave address register, paragraph 53) controlling access to a debug port (debug port, paragraph 53) of the memory device; and a controller (memory subsystem controller 115, figure 2) configured to: receive a signed command to modify access to the debug port (a vendor specific command to memory sub-system 110 to request that debug slave address 246 be enabled, e.g. initialized, paragraph 57); validate the command using a server public key (using a privilege key, authenticate the privilege key; paragraph 57); and update the debug register based on the command (enabling debug slave address 246, paragraph 57). Claims 21 and 28 are substantially similar to claim 1 above. The same grounds of rejection are applied. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2, 22, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mendes as applied to claims 1, 21, and 28 above, further in view of Walmsley (pub # US 20050210179 A1). Regarding claim 2, Mendes discloses debugging for a port but does not disclose explicitly various details of the debug process. However, Walmsley discloses wherein the debug register controls: run-time debugging capabilities including processor halt and single-step execution (CPU halt operation, paragraph 8150); memory access capabilities including read and write permissions (read and write permission, paragraph 1262); and trace capabilities including instruction tracing and data access tracking (error tracking and detection, printed circuit board traces, paragraph 1533). Furthermore, teachings of Mendes and Walmsley are from the same field of port debugging. Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Mendes with Walmsley by using additional debug functions for the benefit of expanding the flexibility of the overall system. Regarding claims 22 and 29, examiner notes these claims are substantially similar to claim 2 above. The same grounds of rejection are applied. Claim(s) 3, 23, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mendes as applied to claims 1, 21, and 28 above, further in view of Yitbarek (pub # US-20200153629-A1). Regarding claim 3, Mendes discloses debugging for a port but does not disclose explicitly various details of the debug process. However, Yitbarek discloses wherein the controller is further configured to: implement an ownership trace feature via the debug port (a trace to find the workload owner, paragraph 37); and identify currently executing processes or tasks of an operating system based on the ownership trace feature (identify workload owner 710, paragraph 37). Furthermore, teachings of Mendes and Yitbarek are from the same field of port debugging. Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Mendes with Yitbarek by using additional debug functions for the benefit of expanding the flexibility of the overall system. Regarding claims 23 and 31, examiner notes these claims are substantially similar to claim 3 above. The same grounds of rejection are applied. Claim(s) 5, 25, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mendes as applied to claims 1, 21, and 28 above, further in view of Dracea (pub #US 20180181480 A1). Regarding claim 5, Mendes discloses debugging for a port but does not disclose explicitly various details of the debug process. However, Dracea discloses wherein the controller is further configured to: receive specifications for breakpoint events (breakpoint and watchpoint events, paragraph 15) including: code execution at specified addresses (instruction addresses, paragraph 15), and data access operations to specified memory locations with specified values (data addresses, paragraph 15); and halt execution when a specified breakpoint event occurs (paragraph 15). Furthermore, teachings of Mendes and ### are from the same field of port debugging. Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Mendes with Dracea by using breakpoint event recording for the benefit of storing information on the breakpoint events for diagnosis (paragraph 15). Regarding claims 25 and 32, examiner notes these claims are substantially similar to claim 5 above. The same grounds of rejection are applied. Regarding claim 6, 26, and 33, Mendes discloses debugging for a port but does not disclose explicitly various details of the debug process. However, examiner takes official notice that on-the-fly memory access, data trace collection; instruction trace collection were well-known debug functions before the effective filing date of the invention, and would have been obvious additions to the overall system for the benefit of expanding system capabilities. Regarding claim 7 and 27, Mendes discloses debugging for a port but does not disclose explicitly various details of the debug process. Examiner takes official notice that maintaining a monotonic counter value; validating received debug commands include monotonically increasing counter values to prevent replay attacks; and implementing memory substitution by replacing internal memory accesses with debug port communications according to received port replacement parameters were well-known debug functions before the effective filing date of the invention, and would have been obvious additions to the overall system for the benefit of expanding system capabilities. Allowable Subject Matter Claim 4, 24, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: prior art of record discloses debug ports and trace functions, but does not disclose using an auxiliary debug port; and the controller implementing ROM patching by redirecting internal memory accesses to fetch instructions from an external debug tool via the auxiliary debug port. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCOTT C SUN/Primary Examiner, Art Unit 2181
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Prosecution Timeline

Oct 25, 2024
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §102, §103
Jul 06, 2026
Response Filed
Oct 12, 2026
Request for Continued Examination
Oct 16, 2026
Response after Non-Final Action
Oct 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+10.7%)
2y 4m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 676 resolved cases by this examiner. Grant probability derived from career allowance rate.

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