DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 04/10/2026. Claims 1-8 and 10-20 are pending. Claims 1, 3-5, 10-11, and 13-18 are amended. Claim 9 is canceled. Examiner notes that at least one amendment to the claims are non-compliant- in claim 18 at line 6 the phrase “responsive to determining” was added without underlining. Applicant is requested to ensure all amendments to the claims are properly indicated.
Response to Arguments
Applicant's arguments filed 04/10/2026 have been fully considered but they are not persuasive.
On page 12 of the Remarks, Applicant submits:
In claim 4, it would be clearly understood by one of ordinary skill in the art that any component of an instruction processing pipeline, including the decoder component and indeed any other part of the execution pipeline, must perform an act of fetching each instruction, whether from storage or from an earlier part of the execution pipeline, as exemplified at least in paragraphs [0041] and [0049].
In claim 18, Applicant respectfully submits that the concept of an eviction suppressor in claim 18 would be well understood by one of ordinary skill in the art, its function being simply to suppress the eviction of a process when invoked in the course of carrying out the method as claimed.
However, these arguments are not persuasive because the term “component” is a generic placeholder, see MPEP 2181 I.A. One of ordinary skill in the art would not understand the specific corresponding structure referred to by a generic “decoder component” or “eviction suppressor component”. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Examiner suggests amending claim 4 to recite a decoder circuit and claim 18 to recite an eviction suppressor circuit to avoid invoking 112(f).
On pages 15-16 of the Remarks, Applicant submits:
Claim 1 has been further amended to recite, in combination with the other limitations of the claim, "in response to determining to enforce the continuation indicator, continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process" (emphasis added). Accordingly, the identification of the hint of Grubisic with the continuation indicator of the present invention is unsuitable, as the continuation indicator has an entirely different function - causing the "continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process," as amended. Grubisic's hint indicates whether a result of an instruction (that is, its data output) may continue to be used, while the continuation indicator of amended claim 1 has no connection with any data output of the instruction, but only with the continued processing in the pipeline.
However, this argument is not persuasive because it does not consider how the references are combined. Grubisic is relied on to modify Sideris to detect the wait modifier when decoding an instruction including the wait modifier. Examiner notes that the amendment to claim 1 “in response to determining to enforce the continuation indicator, continuing to execute the first process…” is still contingent on the determining and is not required under BRI.
On page 16 of the Remarks, Applicant submits:
In particular, the Office Action asserts that the wait modifier of Sideris is evidence of the required continuation indicator. (Office Action, p. 21.) However, the wait modifier of Sideris is not the same as the continuation indicator of amended claim 1. The wait modifier has the technical effect of waiting for a condition before processing the current instruction, whereas the continuation indicator has the technical effect of causing execution of the first instruction and the next sequential instruction without allowing the process to be evicted. (See Sideris 12:35-38.)
However, this argument is not persuasive because claim 1 does not require the continuation indicator to cause execution of the first instruction and next sequential instruction without allowing the process to be evicted, this limitation is contingent on determining to enforce the continuation indicator, which is not required under BRI of the claim. Further, this argument is not persuasive with respect to claim 18 because it only considers Sideris and does not consider how Sideris is modified by Grubisic and Ozer in the rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator” in claim 3, which will be interpreted at a predecoder according to page 14 col 22-24 and page 18 line 30-page 19 line 1 of the specification, or equivalents thereof
“receiving, at the instruction unit… the first process” in claim 4, which will be interpreted as storage according to page 10 lines 1-2 and page 13 lines 23-26 of the specification.
“fetching, with the decoder component… the first instruction” in claim 4. Since the specification does not appear to disclose the specific structure of the decoder component for performing this function, a 112(a)/(b) rejection appears below.
“issuing, from the instruction unit, a work request” in claim 12, which will be interpreted as a scheduler according to page 13 lines 4-6, a message fabric interconnect according to page 19 lines 8-10, or equivalents thereof.
“a client unit to perform the work request” in claim 12, which will be interpreted as a hardware accelerator according to page 9 lines 15-16 or equivalents thereof
“a decoder component to fetch and decode a first instruction of a first process to detect a continuation indicator” in claim 18, which will be interpreted at a predecoder according to page 14 col 22-24 and page 18 line 30-page 19 line 1 of the specification, or equivalents thereof
“an eviction suppressor component… to suppress eviction” in claim 18. Since the specification does not appear to disclose the specific structure of the eviction suppressor component for performing this function, a 112(a)/(b) rejection appears below.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 4-7, 11, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 recites “fetching, with the decoder component… the first instruction” in lines 3-4. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at page 18 lines 29-31 discloses an instruction fetcher to fetch instructions and an instruction pre-decoder that intercepts the incoming instructions, the instruction fetcher is not understood to be a decoder component and the instruction pre-decoder, which is understood to be a decoder component, does not fetch the instructions (since intercepting incoming (i.e., already fetched) instructions is not the same as fetching the instructions). The specification does not disclose the specific structure of a decoder component for fetching an instruction.
Claim 18 recites “an eviction suppressor component… to suppress eviction” in lines 7-8. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at page 16 lines 6-12 discloses an eviction suppressor component, the specification does not disclose the specific structure of the eviction suppressor component for suppressing eviction.
Claims dependent on a rejected base claim are further rejected based on their dependence.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3-7, 11-12, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The rejections corresponding to the 112(f) invocations above appear first.
Claim 4 limitation “fetching, with a decoder component… the first instruction” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at page 18 lines 29-31 discloses an instruction fetcher to fetch instructions and an instruction pre-decoder that intercepts the incoming instructions, the instruction fetcher is not understood to be a decoder component and the instruction pre-decoder, which is understood to be a decoder component, does not fetch the instructions (since intercepting incoming (i.e., already fetched) instructions is not the same as fetching the instructions). The specification does not disclose the specific structure of a decoder component for fetching an instruction. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 18 limitation “an eviction suppressor component to… suppress eviction” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at page 16 lines 6-12 discloses an eviction suppressor component, the specification does not disclose the specific structure of the eviction suppressor component for suppressing eviction. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 3 recites “the detected continuation indicator” in lines 8-9. It is unclear whether this refers to the detected continuation indicator associated with the first instruction (introduced in claim 1) or the detected continuation indicator associated with the second instruction introduced in lines 2-3. For purposes of examination this will be interpreted as referring to the detected continuation indicator associated with the second instruction introduced in line 3.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grubisic US 2021/0124585.
Regarding claim 1, Grubisic teaches:
1) A method of operating a multiprocessor apparatus to process instructions in a pipeline, the method comprising:
fetching a first instruction of a first process ([0048]: instructions are fetched/obtained from memory, the program that a first instruction is a part of (for example, see Fig. 5) is a first process);
decoding the first instruction to detect a continuation indicator associated with the first instruction ([0048] and [0067]: the instruction is decoded to detect a hint associated with the instruction, the hint is a continuation indicator in the sense that it may indicate whether a result of the instruction may continue on to be used, see [0074]); and
in response to determining to enforce the continuation indicator, continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process (since this limitation is contingent on determining to enforce the continuation indicator, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10-12, 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris US 11,276,137 in view of Grubisic US 2021/0124585.
Regarding claim 1, Sideris teaches:
1) A method of operating a multiprocessor apparatus to process instructions in a pipeline, the method comprising:
fetching a first instruction of a first process (col 23 line 63-col 24 line 3: step 44 of Fig. 4 fetches/obtains an instruction of a warp/process);
decoding the first instruction (col 10 lines 27-30: a decode circuit decodes instructions to be executed) including a continuation indicator associated with the first instruction (col 12 lines 34-60: the instructions include a wait modifier which is a continuation indication in the sense that it indicates to not continue execution until one or more conditions are met);
in response to determining to enforce the continuation indicator, continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process (since this limitation is contingent on determining to enforce the continuation indicator, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
While Sideris teaches a decoder and a continuation indicator, Sideris does not teach decoding the first instruction to detect the continuation indicator.
However, Grubisic teaches decoding instructions to detect hint data (analogous to the wait modifier of Sideris), see [0067].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sideris to detect the wait modifier of an instruction by decoding the instruction as taught by Grubisic. One of ordinary skill in the art would have been motivated to make this modification because decoding an instruction is a known technique on the known device of a processor for detecting information in the instruction and would yield the predictable result of enabling the processor to recognize and use the information in the instruction.
Regarding claim 2, Sideris in view of Grubisic teaches:
2) The method of claim 1, wherein continuing comprises suppressing an algorithmically predetermined eviction (this limitation is not required under BRI since it follows from the contingent limitation in claim 1 that is not required under BRI).
Regarding claim 3, Sideris in view of Grubisic teaches:
3) The method of claim 1, comprising:
decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator associated with the second instruction (this limitation is not required under BRI since it follows from there being a second instruction, which is not recited in a required limitation);
in response to determining to enforce the continuation indicator, suppressing eviction of the first process from an instruction unit until completion of the second instruction and at least a next sequential third instruction of the first process responsive to the detected continuation indicator (this limitation is not required under BRI since it is contingent on determining to enforce the continuation indicator of the second instruction, which is not required by the claim).
Regarding claim 4, Sideris in view of Grubisic teaches:
4) The method of claim 3, further comprising,
receiving, at the instruction unit from a control unit, the first process (this limitation is not required under BRI since it follows from there being an instruction unit, which is not recited in a required limitation);
fetching, with the decoder component from the control unit, the first instruction of the first process (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation).
Regarding claim 5, Sideris in view of Grubisic teaches:
5) The method of claim 4, further comprising:
obtaining, from the control unit, additional information associated with the first instruction (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation), where the additional information comprises one or more of: a position of the first instruction in cache; a type of the current and next sequential second instruction; a termination condition; a dependency condition; a priority level for the first instruction.
Regarding claim 6, Sideris in view of Grubisic teaches:
6) The method of claim 5, comprising:
identifying an eviction point for the first instruction based on or in response to the additional information associated with the first instruction (this limitation is not required under BRI since it is contingent on the additional information, which is not recited in a required limitation).
Regarding claim 7, Sideris in view of Grubisic teaches:
7) The method of claim 6, further comprising:
evicting the first process from the instruction unit at completion of the first instruction in response to the identified eviction point (this limitation is not required under BRI since it follows from there being an instruction unit and is contingent on the identified eviction point, which is not required by the claim).
Regarding claim 10, Sideris in view of Grubisic teaches:
10) The method of claim 1, further comprising:
storing instructions of the first process in a first storage at a first pipeline stage (Sideris col 13 lines 58-62: instructions are allocated into a respective instruction buffer for execution by the respective execution thread group, the respective instruction buffer that stores instructions of the first process/thread group is a first storage at a first pipeline stage);
storing instructions of a second process in a second storage at the first pipeline stage (Sideris col 13 lines 58-62: instructions are allocated into a respective instruction buffer for execution by the respective execution thread group, the respective instruction buffer that stores instructions of a second process/thread group is a second storage at the first pipeline stage);
selecting instructions from the first and/or second storage (Sideris col 13 lines 58-62: the instructions are allocated into a respective instruction buffer of the execution unit for execution by the respective execution thread group, which indicates that the execution unit selects instructions from the respective instruction buffer for execution); and
issuing, to a second pipeline stage, the selected instructions as an instruction stream for processing (Sideris col 13 lines 58-62: the instructions are allocated into a respective instruction buffer of the execution unit for execution by the respective execution thread group, which indicates that the instructions are issued to the execution units (i.e., a second pipeline stage) and the set of instructions issued from the instruction buffer to the execution unit is an instruction stream).
Regarding claim 11, Sideris in view of Grubisic teaches:
11) The method of claim 7, where evicting the first process from the instruction unit at completion of the first instruction comprises:
returning the first process to a work queue at the control unit for selection by a scheduler (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation).
Regarding claim 12, Sideris in view of Grubisic teaches:
12) The method of claim 3, further comprising:
issuing, from the instruction unit, a work request to a client unit to perform the work request in accordance with the first instruction (this limitation is not required under BRI since it follows from there being an instruction unit, which is not recited in a required limitation).
Regarding claim 14, Sideris in view of Grubisic teaches:
14) The method of claim 1, wherein when the continuation indicator is not detected:
evicting the first process from an instruction unit at completion of the first instruction (this limitation is not required under BRI since it is contingent on not detecting a continuation indicator, which is not required by the claim).
Regarding claim 15, Sideris in view of Grubisic teaches:
15) The method of claim 13, comprising:
receiving, from a control unit (Sideris Fig. 3, icache 35 and scheduler 36), a further process when the first process is evicted (Sideris col 23 lines 13-20: when a thread group/process is evicted, a further thread group/process takes its place fetching instructions into the execution buffer, which includes receiving the further thread group/process from the scheduler 35 (see Fig. 3 “warp issue”) and instructions from the icache).
Regarding claim 16, Sideris in view of Grubisic teaches:
16) The method of claim 1, where the continuation indicator is encoded in the first instruction (Sideris col 3 lines 62-67: the wait modifier is part of the instruction itself, i.e., encoded in the instruction).
Regarding claim 17, Sideris in view of Grubisic teaches:
17) The method of claim 1, wherein at least one of the first process and a second process comprises a warp (Sideris col 23 line 63-col 24 line 3: the thread groups are warps).
Regarding claim 19, Sideris in view of Grubisic teaches:
19) A computer program comprising computer program code to, when loaded into a processor and executed thereon, cause the processor to perform the method of claim 1 (col 17 lines 1-10: the method may be implemented as computer software code executed on a processor).
Regarding claim 20, Sideris in view of Grubisic teaches:
20) A computer program operable to adapt a host processing system to provide an execution environment permitting operation of non-native processor instructions to perform the method of claim 1 (col 18 lines 1-15: the host processor provides graphics processor 3 (i.e., an execution environment) permitting operation of commands/non-native processor instructions, which control the graphics processor to perform the method of claim 1).
Claims 8, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris US 11,276,137 in view of Grubisic US 2021/0124585 and Ozer US 2008/0270749.
Regarding claim 8, Sideris in view of Grubisic teaches:
8) The method of claim 1, further comprising:
storing instructions of the first process and instructions of a second process in storage at a first pipeline stage (Siberis col 22 lines 53-59 and col 23 lines 13-20: instruction execution buffer 41 (i.e., storage at a first pipeline stage) stores instructions of a process/thread group and when that process is evicted another thread group/process takes its place fetching instructions to store in the buffer);
issuing, to a second pipeline stage, the instructions of the first and second processes (Siberis col 22 lines 60-64: instructions from the execution buffer are fetched/issued to the execution unit (i.e., a second pipeline stage), which includes the instructions of the first process before it is evicted and the instructions of the second process the replaces the first process)
Sideris in view of Grubisic does not teach:
issuing, to a second pipeline stage, the instructions of the first and second processes in an interleaved instruction stream.
However, Ozer teaches issuing instructions of a first and second process in an interleaved instruction stream ([0052]: thread interleaving circuitry forms an interleaved stream of instructions from different threads which are issued to a shared issue queue).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the system of Sideris in view of Grubisic to include thread interleaving circuitry to issue instructions of a first and second process in an interleaved instruction stream to a shared issue queue as taught by Ozer. One of ordinary skill in the art would have been motivated to make this modification to enable issuing instructions in parallel from different threads with reduced complexity and overhead (Ozer [0015]).
Regarding claim 13, Sideris in view of Grubisic teaches:
13) The method of claim 1,
Although Sideris teaches evicting a process at completion of an instruction, see col 24 lines 49-55, Sideris does so when enforcing a “wait” indicator that flags when there are dependent instructions. That is, Sideris in view of Grubisic does not teach:
wherein when it is determined not to enforce the continuation indicator:
evicting the first process from an instruction unit at completion of the first instruction.
However, Ozer teaches using hints (analogous to the wait modifier) to indicate instructions that have no data dependence and are capable of parallel issue, see [0056].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the wait indicator of Sideris in view of Grubisic to instead indicate instructions that have no data dependence as taught by Ozer such that the combination would enforce the hint by continuing execution of processes that have no dependence and would not enforce the hint by evicting processes at completion of the instruction. One of ordinary skill in the art would have been motivated to make this modification to reduce the overhead of encoding instruction dependence indicators when there are lesser independent instructions than dependent instructions.
Regarding claim 18, Sideris teaches:
18) A multiprocessing apparatus operable to process instructions in a pipeline, comprising:
a decoder component to fetch and decode a first instruction of a first process (col 10 lines 27-30: a decode circuit fetches and decodes instructions to be executed, the decoder circuit and eviction circuit 39 of Fig. 3 are collectively a decoder component) including a continuation indicator associated with the first instruction (col 12 lines 34-60: the instructions include a wait modifier which is a continuation indication in the sense that it indicates to not continue execution until one or more conditions are met);
an eviction suppressor component to suppress eviction of the first process from an instruction unit to continue processing until completion of the first instruction and at least a next second sequential instruction of the first process (col 23 lines 28-53: the external dependency check unit 40 is an eviction suppressor component that suppresses eviction of a process by determining when it is safe to continue fetching without evicting the thread group/process, which suppresses eviction of the process from the instruction buffer (i.e., an instruction unit) to continue processing until completion of the instruction and a next instruction, see col 24 lines 44-48).
Sideris does not teach:
the decoder component decoding the first instruction to detect the continuation indicator;
the eviction suppressor component suppressing eviction responsive to determining to enforce the continuation indicator.
However, Grubisic teaches decoding instructions to detect hint data (analogous to the wait modifier of Sideris), see [0067].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sideris to detect the wait modifier of an instruction by decoding the instruction as taught by Grubisic. One of ordinary skill in the art would have been motivated to make this modification because decoding an instruction is a known technique on the known device of a processor for detecting information in the instruction and would yield the predictable result of enabling the processor to recognize and use the information in the instruction.
The combination of Sideris in view of Grubisic does not teach:
the eviction suppressor component suppressing eviction responsive to determining to enforce the continuation indicator.
However, Ozer teaches using hints (analogous to the wait modifier in Sideris in that it also encodes dependency information) to indicate instructions that have no data dependence and are capable of parallel issue, see [0056].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the wait indicator of Sideris (which indicates instructions that have a dependence) in view of Grubisic to instead indicate instructions that have no data dependence as taught by Ozer such that the combination would enforce the hint by suppressing eviction/continuing execution of processes that have no dependence (as Sideris suppresses eviction and continues execution when there is no dependence, see col 23 lines 28-53). In other words, the hint/indication of no data dependence of the combination is a continuation indicator in that it is an indication to suppress eviction/continue executing and the eviction suppressor of the combination would enforce this hint by suppressing eviction and continuing execution. One of ordinary skill in the art would have been motivated to make this modification to reduce the overhead of encoding instruction dependence indicators when there are lesser independent instructions than dependent instructions.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183
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