DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2025 and 11/11/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
Figures 1A, 2, and 3 are objected to under 37 CFR 1.84(o), suitable descriptive legends are required for properly understanding these drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator” in claim 3, which will be interpreted at a predecoder according to page 14 col 22-24 and page 18 line 30-page 19 line 1 of the specification, or equivalents thereof
“determining, with the decoder component, whether or not to enforce the continuation indicator” in claim 3. Since the specification does not appear to disclose the specific structure of the decoder component for performing this function, a 112(a)/(b) rejection appears below.
“receiving, at the instruction unit… the first process” in claim 4, which will be interpreted as storage according to page 10 lines 1-2 and page 13 lines 23-26 of the specification.
“fetching, with a decoder component… the first instruction” in claim 4. Since the specification does not appear to disclose the specific structure of the decoder component for performing this function, a 112(a)/(b) rejection appears below.
“issuing, from the instruction unit, a work request” in claim 12, which will be interpreted as a scheduler according to page 13 lines 4-6, a message fabric interconnect according to page 19 lines 8-10, or equivalents thereof.
“a client unit to perform the work request” in claim 12, which will be interpreted as a hardware accelerator according to page 9 lines 15-16 or equivalents thereof
“a receiver component for obtaining a first instruction” in claim 18, which will be interpreted as an instruction fetcher according to page 18 lines 29-30 of the specification
“a decoder component to decode a first instruction of a first process to detect a continuation indicator” in claim 18, which will be interpreted at a predecoder according to page 14 col 22-24 and page 18 line 30-page 19 line 1 of the specification, or equivalents thereof
“an eviction suppressor component to… suppress eviction” in claim 18. Since the specification does not appear to disclose the specific structure of the eviction suppressor component for performing this function, a 112(a)/(b) rejection appears below.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 3-5 are objected to because of the following informalities:
claim 3 line 9- insert --first-- before “process” to clarify that this refers to the first process introduced in claim 1
claim 4 line 4- replace “for” with --of-- to be consistent with the phrasing used in claim 1 line 3
claim 5 line 3- “the position” should be --a position--
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 3-7 and 11-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 recites “determining, with the decoder component, whether or not to enforce the continuation indicator” in lines 5-6. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at page 14 lines 22-25 discloses a decoder component 134 and page 18 lines 3-8 discloses that the execution engine 100 can determine whether or not to act in accordance with the value of the continuation indicator, the decoder component 134 is shown to be a component within the execution engine 100 in Figure 3 and the specification does not disclose the specific structure of the decoder component for performing this function.
Claim 4 recites “fetching, with a decoder component… the first instruction” in lines 3-4. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at page 18 lines 29-31 discloses an instruction fetcher to fetch instructions and an instruction pre-decoder that intercepts the incoming instructions, the instruction fetcher is not understood to be a decoder component and the instruction pre-decoder, which is understood to be a decoder component, does not fetch the instructions (since intercepting incoming (i.e., already fetched) instructions is not the same as fetching the instructions). The specification does not disclose the specific structure of a decoder component for fetching an instruction.
Claim 18 recites “an eviction suppressor component to… suppress eviction” in lines 7-8. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at page 16 lines 6-12 discloses an eviction suppressor component, the specification does not disclose the specific structure of the eviction suppressor component for suppressing eviction.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3-7, 9, 11-12, and 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The rejections corresponding to the 112(f) invocations above appear first.
Claim 3 limitation “determining, with the decoder component, whether or not to enforce the continuation indicator” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at page 14 lines 22-25 discloses a decoder component 134 and page 18 lines 3-8 discloses that the execution engine 100 can determine whether or not to act in accordance with the value of the continuation indicator, the decoder component 134 is shown to be a component within the execution engine 100 in Figure 3 and the specification does not disclose the specific structure of the decoder component for performing this function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 4 limitation “fetching, with a decoder component… the first instruction” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at page 18 lines 29-31 discloses an instruction fetcher to fetch instructions and an instruction pre-decoder that intercepts the incoming instructions, the instruction fetcher is not understood to be a decoder component and the instruction pre-decoder, which is understood to be a decoder component, does not fetch the instructions (since intercepting incoming (i.e., already fetched) instructions is not the same as fetching the instructions). The specification does not disclose the specific structure of a decoder component for fetching an instruction. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 18 limitation “an eviction suppressor component to… suppress eviction” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at page 16 lines 6-12 discloses an eviction suppressor component, the specification does not disclose the specific structure of the eviction suppressor component for suppressing eviction. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 3 recites “a detected continuation indicator” in line 9. It is unclear whether this is the same as the detected continuation indicator associated with the second instruction introduced in line 3, the detected continuation indicator associated with the first instruction introduced in claim 1 line 4, or if it is a different detected continuation indicator. For purposes of examination this will be interpreted as referring to the detected continuation indicator associated with the second instruction introduced in line 3.
Claim 4 recites “a decoder component” in line 3. It is unclear whether this is the same as the decoder component introduced in claim 3 line 2 or if they are different. For purposes of examination, they will be interpreted as referring to the same decoder component.
Claim 5 recites “the type of the current and next sequential second instruction” in line 4. There is insufficient antecedent basis for this limitation as the claim does not introduce a current instruction having a type of the next sequential second instruction having a type.
Claim 9 recites “wherein the determining detects an “always continue” indication and always continues to execute the first process” in lines 1-2 and claim 1 recites “determining whether or not to enforce the continuation indicator” in line 6. However, the specification at page 12 lines 22-26 and page 18 lines 3-8 indicates that these are separate embodiments- the continuation indicator is either determinative and always functions in accordance with the value of the CI (i.e., the CI is an “always continue” indicator”) or the CI is indicative and may be ignored/not enforced. Thus, while this limitation may be clear on its face, it renders the claim indefinite because of the inconsistency with the specification. See MPEP 2173.03. Further, the wording of this limitation indicates that the determining step itself executes the first process. It is unclear how the determining step itself can execute a process since performing a determination is not understood to be a way for executing a process. For purposes of examination this limitation will be interpreted as detecting an “always continue” indication to always continue executing the first process.
Claim 9 recites “a next sequential second instruction of the first process” in lines 3-4. It is unclear whether this refers to the same next sequential second instruction of the first process introduced in the last line of claim 1 or if they are different. For purposes of examination this limitation will be interpreted as referring to the same next sequential second instruction introduced in claim 1.
Claim 11 recites “The method of claim 6, where evicting the first process from the instruction unit at completion of the first instruction comprises […]” in lines 1-2. The use of the transitional word “where” is understood to refer to a previously introduced step. However, the claim does not previously introduce the step of evicting the first process, so it does not make sense to say “The method of claim 6, where evicting the first process”. For purposes of examination, this limitation will be interpreted as depending from claim 7, which does introduce an “evicting the first process” step.
Claim 13 recites “the instruction unit” in line 3. There is insufficient antecedent basis for this limitation as the claim does not previously introduce an instruction unit.
Claim 14 recites “a continuation indicator” in line 1. It is unclear whether this refers to the continuation indicator introduced in claim 1 or if it is different. For purposes of examination this will be interpreted as referring to a different continuation indicator.
Claim 14 recites “the instruction unit” in line 1. There is insufficient antecedent basis for this limitation as the claim does not previously introduce an instruction unit.
Claim 15 recites “the control unit” in line 2. There is insufficient antecedent basis for this limitation as the claim does not previously introduce a control unit.
Claim 16 recites “the instruction” in lines 1-2. It is unclear whether this refers to the first instruction or the second instruction introduced in claim 1. For purposes of examination this will be interpreted as referring to the first instruction.
Claim 17 recites “the first and the second processes” in lines 1-2. There is insufficient antecedent basis for this limitation since the claim does not previously introduce a second process.
Claim 18 recites “a first instruction of a first process” in line 4. It is unclear whether this refers to the same instruction and process introduced in lines 1-2 or if they are different. For purposes of examination, they will be interpreted as the same.
Claim 18 recites “the first instruction” in line 5 and line 5. It is unclear whether these refer to the first instruction introduced in line 2 or line 4.
Claim 18 recites “the first process” in line 8 and line 10. It is unclear whether these refer to the first process introduced in lines 2-3 or line 4.
Claim 18 recites “the instruction unit” in lines 8-9. There is insufficient antecedent basis for this limitation as the claim does not introduce an instruction unit.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7, 11-12, 14, 16-17, and 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites:
1) A computer implemented method for processing instructions in a multiprocessing apparatus, the method comprising:
obtaining a first instruction of a first process;
decoding the first instruction to detect a continuation indicator associated with the first instruction;
determining whether or not to enforce the continuation indicator;
when it is determined to enforce the continuation indicator:
continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process.
Examiner notes that since the claim is directed to a method, the contingent limitation “when it is determined to enforce the continuation indication: continuing to execute…” is not required under BRI, see MPEP 2111.04(II).
The claim is directed to the abstract idea of a mental process (Step 2A Prong One, Yes) because a person can mentally perform the step of determining whether or not to enforce a continuation indicator. The claim recites the additional elements of “obtaining a first instruction of a first process” and “decoding the first instruction to detect a continuation indicator…”. However, the additional elements amount to the mere use of a generic computer as a tool to perform the abstract idea, as obtaining and decoding instructions are generic computer functions. The additional elements are generically recited computer elements that do not add a meaningful limitation to the abstract idea because they amount to simply implementing the abstract idea on a computer. They do not alone or in combination integrate the abstract idea into a practical application (Step 2A Prong Two, No). At Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for step 2A.
Claim 2 recites “wherein continuing comprises suppressing an algorithmically predetermined eviction”. However, this limitation follows from the contingent limitation of claim 1 and is not required under BRI. Thus, claim 2 does not recite additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 3 recites:
3) The method of claim 1, comprising:
decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator associated with the second instruction;
determining, with the decoder component, whether or not to enforce the continuation indicator of the second instruction; and
suppressing eviction of the first process from an instruction unit until completion of the second instruction and at least a next sequential third instruction of the process responsive to a detected continuation indicator when it is determined to enforce the continuation indicator of the second instruction.
The step of decoding the second instruction is not required under BRI since it follows from there being a second instruction, which is not required in claim 1 (i.e., claim 1 only recites the second instruction contingently). The step of determining whether or not to enforce the continuation indicator of the second instruction is also not required under BRI since it also follows from there being a second instruction, which is not required in claim 1. The step of suppressing eviction of the first process until completion of the second instruction is also not required under BRI since it also follows from there being a second instruction, which is not required in claim 1, and since it is also a contingent limitation (contingent on determining to enforce the continuation indicator of the second instruction). Since the limitations of claim 3 are not required under BRI, claim 3 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 4 recites:
receiving, at the instruction unit from a control unit, the first process;
fetching, with a decoder component from the control unit, the first instruction for the first process.
The step of receiving the first process at the instruction unit is not required under BRI since it follows from there being an instruction unit, which is not required in claim 3 (i.e., claim 3 only recites the instruction unit contingently). The step of fetching the first instruction from the control unit is also not required under BRI since it follows from there being a control unit, which is not required by the claim. Since the limitations of claim 4 are not required under BRI, claim 4 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 5 recites “obtaining, from the control unit, additional information…”. However, this step is not required under BRI since it follows from there being a control unit, which is not required by the claims. Since the limitations of claim 5 are not required under BRI, claim 5 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 6 recites “identifying an eviction point for the first instruction based on or in response to the additional information…”. However, this step is not required under BRI since it is contingent on there being additional information, which is not required by the claim. Since the limitations of claim 6 are not required under BRI, claim 6 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 7 recites “evicting the first process from the instruction unit at completion of the first instruction in response to the identified eviction point”. However, this step is not required under BRI since it is contingent on identifying the eviction point, which is not required by the claim. Since the limitations of claim 7 are not required under BRI, claim 7 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 11 recites “where evicting the first process… comprises: returning the first process to a work queue at the control unit…”. However, this step is not required under BRI since it follows from there being a control unit, which is not required by the claims. Since the limitations of claim 11 are not required under BRI, claim 11 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 12 recites “issuing, from the instruction unit, a work request…”. However, this step is not required under BRI since it follows from there being an instruction unit, which is not required in claim 3 (i.e., claim 3 only recites the instruction unit contingently). Since the limitations of claim 12 are not required under BRI, claim 12 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 14 recites “wherein when a continuation indicator is not detected: evicting the first process…”. However, this step is not required under BRI since it is contingent on a continuation indicator not being detected, which is not required by the claims (i.e., the claims do not require a continuation indicator to not be detected). Since the limitations of claim 14 are not required under BRI, claim 14 does not recite any additional elements that would integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 16 recites “where the continuation indicator is encoded in the instruction”. However, this limitation merely describes the encoding of the instruction, which still amounts to the mere use of a generic computer as a tool to perform the abstract idea, since decoding an instruction with encoded information is a generic computer function. Thus, this additional element does not integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 17 recites “wherein at least one of the first and second processes comprises a warp. However, this limitation merely describes the process that the first instruction is part of, which still amounts to the mere use of a generic computer as a tool to perform the abstract idea, since decoding an instruction of a process that is a warp is a generic computer function. Thus, this additional element does not integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim 19 recites “A computer program comprising computer program code to, when loaded into a processor and executed thereon, cause the processor to perform the method of claim 1.” This additional element amounts to the mere use of a generic computer as a tool to perform the abstract idea, since a processor executing a computer program is a generic computer function. Thus, this additional element does not integrate the abstract idea into a practical application or amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grubisic US 2021/0124585.
Regarding claim 1, Grubisic teaches:
1) A computer implemented method for processing instructions in a multiprocessing apparatus, the method comprising:
obtaining a first instruction of a first process ([0048]: instructions are fetched/obtained from memory, the program that a first instruction is a part of (for example, see Fig. 5) is a first process);
decoding the first instruction to detect a continuation indicator associated with the first instruction ([0048] and [0067]: the instruction is decoded to detect a hint associated with the instruction, the hint is a continuation indicator in the sense that it may indicate whether a result of the instruction may continue on to be used, see [0074]);
determining whether or not to enforce the continuation indicator ([0064]: the processor may use/enforce the hint or ignore/not enforce the hint);
when it is determined to enforce the continuation indicator:
continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process (since this limitation is contingent on determining to enforce the continuation indicator, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-12, 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris US 11,276,137 in view of Grubisic US 2021/0124585.
Regarding claim 1, Sideris teaches:
1) A computer implemented method for processing instructions in a multiprocessing apparatus, the method comprising:
obtaining a first instruction of a first process (col 23 line 63-col 24 line 3: step 44 of Fig. 4 fetches/obtains an instruction of a warp/process);
decoding the first instruction (col 10 lines 27-30: a decode circuit decodes instructions to be executed) including a continuation indicator associated with the first instruction (col 12 lines 34-60: the instructions include a wait modifier which is a continuation indication in the sense that it indicates to not continue execution until one or more conditions are met);
determining whether or not to enforce the continuation indicator (col 12 lines 34-60 and col 24 lines 39-44: the wait modifier causes the execution unit to determine whether to evict the warp or continue execution, which discloses determining whether or not to enforce the wait modifier/ continuation indicator since the wait modifier is enforced when the warp is evicted and is ignored/not enforced when execution is continued, see also col 14 lines 52-60);
when it is determined to enforce the continuation indicator:
continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process (since this limitation is contingent on determining to enforce the continuation indicator, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
While Sideris teaches a decoder and a continuation indicator, Sideris does not teach decoding the first instruction to detect the continuation indicator.
However, Grubisic teaches decoding instructions to detect hint data (analogous to the wait modifier of Sideris), see [0067].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sideris to detect the wait modifier of an instruction by decoding the instruction as taught by Grubisic. One of ordinary skill in the art would have been motivated to make this modification because decoding an instruction is a known technique on the known device of a processor for detecting information in the instruction and would yield the predictable result of enabling the processor to recognize and use the information in the instruction.
Regarding claim 2, Sideris in view of Grubisic teaches:
2) The method of claim 1, wherein continuing comprises suppressing an algorithmically predetermined eviction (this limitation is not required under BRI since it follows from the contingent limitation in claim 1 that is not required under BRI).
Regarding claim 3, Sideris in view of Grubisic teaches:
3) The method of claim 1, comprising:
decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator associated with the second instruction (this limitation is not required under BRI since it follows from there being a second instruction, which is not recited in a required limitation);
determining, with the decoder component, whether or not to enforce the continuation indicator of the second instruction (this limitation is not required under BRI since it follows from there being a decoder component, which is not recited in a required limitation); and
suppressing eviction of the first process from an instruction unit until completion of the second instruction and at least a next sequential third instruction of the process responsive to a detected continuation indicator when it is determined to enforce the continuation indicator of the second instruction (this limitation is not required under BRI since it is contingent on determining to enforce the continuation indicator of the second instruction, which is not required by the claim).
Regarding claim 4, Sideris in view of Grubisic teaches:
4) The method of claim 3, further comprising,
receiving, at the instruction unit from a control unit, the first process (this limitation is not required under BRI since it follows from there being an instruction unit, which is not recited in a required limitation);
fetching, with a decoder component from the control unit, the first instruction for the first process (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation).
Regarding claim 5, Sideris in view of Grubisic teaches:
5) The method of claim 4, further comprising:
obtaining, from the control unit, additional information associated with the first instruction (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation), where the additional information comprises one or more of: the position of the first instruction in cache; the type of the current and next sequential second instruction; a termination condition; a dependency condition; a priority level for the first instruction.
Regarding claim 6, Sideris in view of Grubisic teaches:
6) The method of claim 5, comprising:
identifying an eviction point for the first instruction based on or in response to the additional information associated with the first instruction (this limitation is not required under BRI since it is contingent on the additional information, which is not recited in a required limitation).
Regarding claim 7, Sideris in view of Grubisic teaches:
7) The method of claim 6, further comprising:
evicting the first process from the instruction unit at completion of the first instruction in response to the identified eviction point (this limitation is not required under BRI since it follows from there being an instruction unit and is contingent on the identified eviction point, which is not required by the claim).
Regarding claim 9, Sideris in view of Grubisic teaches:
9) The method according to claim 1, wherein the determining detects an “always continue” indication and always continues to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process (Sideris col 24 lines 39-48: the determination at step 49 that the warp does not need to be evicted is an “always continue” indication to always continue executing the first process by pushing the instruction to the instruction buffer for execution and fetching the next instruction (i.e., until completion of the first instruction and a next sequential second instruction of the process)).
Regarding claim 10, Sideris in view of Grubisic teaches:
10) The method of claim 1, further comprising:
storing instructions of the first process in a first storage at a first pipeline stage (Sideris col 13 lines 58-62: instructions are allocated into a respective instruction buffer for execution by the respective execution thread group, the respective instruction buffer that stores instructions of the first process/thread group is a first storage at a first pipeline stage);
storing instructions of a second process in a second storage at the first pipeline stage (Sideris col 13 lines 58-62: instructions are allocated into a respective instruction buffer for execution by the respective execution thread group, the respective instruction buffer that stores instructions of a second process/thread group is a second storage at the first pipeline stage);
selecting instructions from the first and/or second storage (Sideris col 13 lines 58-62: the instructions are allocated into a respective instruction buffer of the execution unit for execution by the respective execution thread group, which indicates that the execution unit selects instructions from the respective instruction buffer for execution);
issuing, to a second pipeline stage, the selected instructions as an instruction stream for processing (Sideris col 13 lines 58-62: the instructions are allocated into a respective instruction buffer of the execution unit for execution by the respective execution thread group, which indicates that the instructions are issued to the execution units (i.e., a second pipeline stage) and the set of instructions issued from the instruction buffer to the execution unit is an instruction stream).
Regarding claim 11, Sideris in view of Grubisic teaches:
11) The method of claim 6, where evicting the first process from the instruction unit at completion of the first instruction comprises:
returning the first process to a work queue at the control unit for selection by a scheduler (this limitation is not required under BRI since it follows from there being a control unit, which is not recited in a required limitation).
Regarding claim 12, Sideris in view of Grubisic teaches:
12) The method of claim 3, further comprising:
issuing, from the instruction unit, a work request to a client unit to perform the work request in accordance with the first instruction (this limitation is not required under BRI since it follows from there being an instruction unit, which is not recited in a required limitation).
Regarding claim 14, Sideris in view of Grubisic teaches:
14) The method of claim 1, wherein when a continuation indicator is not detected:
evicting the first process from the instruction unit at completion of the first instruction (this limitation is not required under BRI since it is contingent on not detecting a continuation indicator, which is not required by the claim).
Regarding claim 15, Sideris in view of Grubisic teaches:
15) The method of claim 13, comprising:
receiving, from the control unit (Sideris Fig. 3, icache 35 and scheduler 36), a further process when the first process is evicted (Sideris col 23 lines 13-20: when a thread group/process is evicted, a further thread group/process takes its place fetching instructions into the execution buffer, which includes receiving the further thread group/process from the scheduler 35 (see Fig. 3 “warp issue”) and instructions from the icache).
Regarding claim 16, Sideris in view of Grubisic teaches:
16) The method of claim 1, where the continuation indicator is encoded in the instruction (Sideris col 3 lines 62-67: the wait modifier is part of the instruction itself, i.e., encoded in the instruction).
Regarding claim 17, Sideris in view of Grubisic teaches:
17) The method of claim 1, wherein at least one of the first and the second processes comprises a warp (Sideris col 23 line 63-col 24 line 3: the thread groups are warps).
Regarding claim 19, Sideris in view of Grubisic teaches:
19) A computer program comprising computer program code to, when loaded into a processor and executed thereon, cause the processor to perform the method of claim 1 (col 17 lines 1-10: the method may be implemented as computer software code executed on a processor).
Regarding claim 20, Sideris in view of Grubisic teaches:
20) A computer program operable to adapt a host processing system to provide an execution environment permitting operation of non-native processor instructions to perform the method of claim 1 (col 18 lines 1-15: the host processor provides graphics processor 3 (i.e., an execution environment) permitting operation of commands/non-native processor instructions, which control the graphics processor to perform the method of claim 1).
Claims 8, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris US 11,276,137 in view of Grubisic US 2021/0124585 and Ozer US 2008/0270749
Regarding claim 8, Sideris in view of Grubisic teaches:
8) The method of claim 1, further comprising:
storing instructions of the first process and instructions of a second process in storage at a first pipeline stage (Siberis col 22 lines 53-59 and col 23 lines 13-20: instruction execution buffer 41 (i.e., storage at a first pipeline stage) stores instructions of a process/thread group and when that process is evicted another thread group/process takes its place fetching instructions to store in the buffer);
issuing, to a second pipeline stage, the instructions of the first and second processes (Siberis col 22 lines 60-64: instructions from the execution buffer are fetched/issued to the execution unit (i.e., a second pipeline stage), which includes the instructions of the first process before it is evicted and the instructions of the second process the replaces the first process)
Sideris in view of Grubisic does not teach:
issuing, to a second pipeline stage, the instructions of the first and second processes in an interleaved instruction stream.
However, Ozer teaches issuing instructions of a first and second process in an interleaved instruction stream ([0052]: thread interleaving circuitry forms an interleaved stream of instructions from different threads which are issued to a shared issue queue).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the system of Sideris in view of Grubisic to include thread interleaving circuitry to issue instructions of a first and second process in an interleaved instruction stream to a shared issue queue as taught by Ozer. One of ordinary skill in the art would have been motivated to make this modification to enable issuing instructions in parallel from different threads with reduced complexity and overhead (Ozer [0015]).
Regarding claim 13, Sideris in view of Grubisic teaches:
13) The method of claim 1,
Although Sideris teaches evicting a process at completion of an instruction, see col 24 lines 49-55, Sideris does so when enforcing a “wait” indicator that flags when there are dependent instructions. That is, Sideris in view of Grubisic does not teach:
wherein when it is determined not to enforce the continuation indicator:
evicting the first process from the instruction unit at completion of the first instruction.
However, Ozer teaches using hints (analogous to the wait modifier) to indicate instructions that have no data dependence and are capable of parallel issue, see [0056].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the wait indicator of Sideris in view of Grubisic to instead indicate instructions that have no data dependence as taught by Ozer such that the combination would enforce the hint by continuing execution of processes that have no dependence and would not enforce the hint by evicting processes at completion of the instruction. One of ordinary skill in the art would have been motivated to make this modification to reduce the overhead of encoding instruction dependence indicators when there are lesser independent instructions than dependent instructions.
Regarding claim 18, Sideris teaches:
18) A multiprocessing apparatus operable to process instructions, comprising:
a receiver component for obtaining a first instruction of a first process (col 22 lines 53-57 and col 23 line 63-col 24 line 3: step 44 of Fig. 4 fetches/obtains an instruction of a warp/process using a fetch unit/receiver component);
a decoder component to decode a first instruction of a first process (col 10 lines 27-30: a decode circuit decodes instructions to be executed, the decoder circuit and eviction circuit 39 of Fig. 3 are collectively a decoder component) including a continuation indicator associated with the first instruction (col 12 lines 34-60: the instructions include a wait modifier which is a continuation indication in the sense that it indicates to not continue execution until one or more conditions are met) and to determine whether or not to enforce the continuation indicator thereof (col 12 lines 34-60, col 23 lines 10-12, and col 24 lines 39-44: the wait modifier causes an eviction circuit to determine whether to evict the warp or continue execution, which discloses determining whether or not to enforce the wait modifier/ continuation indicator since the wait modifier is enforced when the warp is evicted and is ignored/not enforced when execution is continued, see also col 14 lines 52-60);
an eviction suppressor component to suppress eviction of the first process from the instruction unit to continue processing until completion of the first instruction and at least a next second sequential instruction of the first process (col 23 lines 28-53: the external dependency check unit 40 is an eviction suppressor component that suppresses eviction of a process by determining when it is safe to continue fetching without evicting the thread group/process, which suppresses eviction of the process from the instruction buffer (i.e., an instruction unit) to continue processing until completion of the instruction and a next instruction, see col 24 lines 44-48).
Sideris does not teach:
the decoder component decoding the first instruction to detect the continuation indicator;
the eviction suppressor component suppressing eviction when it is determined to enforce the continuation indicator.
However, Grubisic teaches decoding instructions to detect hint data (analogous to the wait modifier of Sideris), see [0067].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sideris to detect the wait modifier of an instruction by decoding the instruction as taught by Grubisic. One of ordinary skill in the art would have been motivated to make this modification because decoding an instruction is a known technique on the known device of a processor for detecting information in the instruction and would yield the predictable result of enabling the processor to recognize and use the information in the instruction.
The combination of Sideris in view of Grubisic does not teach:
the eviction suppressor component suppressing eviction when it is determined to enforce the continuation indicator.
However, Ozer teaches using hints (analogous to the wait modifier) to indicate instructions that have no data dependence and are capable of parallel issue, see [0056].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the wait indicator of Sideris in view of Grubisic to instead indicate instructions that have no data dependence as taught by Ozer such that the combination would enforce the hint by suppressing eviction/continuing execution of processes that have no dependence. One of ordinary skill in the art would have been motivated to make this modification to reduce the overhead of encoding instruction dependence indicators when there are lesser independent instructions than dependent instructions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,954,715 teaches interleaving threads to perform fine grained multithreading and using performance values to determine which program thread is selected next when a thread switch event occurs, see Abstract
US 5,941,983 teaches out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issuance of instructions from the queues
US 8,108,859 teaches switching threads when there is an instruction cache miss or when thread execution priority changes, see Abstract
US 2025/0123845 teaches segmenting an instruction stream to multiple instruction queues by marking an instruction at the segmentation boundary, see [0077]
US 2005/0149931 teaches instructions having a thread switching trigger data field that is used to trigger thread switches, see Abstract
US 2013/0332711 teaches designating one or more bits of an instruction payload as a context switch bit for expressly controlling context switching, see Abstract
US 6,697,935 teaches thread switch logic that forces a thread switch after a programmable period of time, prevents repetitive thread switching, and changes the priority of threads to supersede thread switch events, see Abstract
US 2017/0132011 teaches using an execution hint instruction to indicate an expected delay so that execution may switch to another thread, see [0002]
US 2017/0315806 teaches inserting a wait instruction upon determining that a thread depends on a condition variable and continuing execution of the thread if the variable updates before a timeout period of the wait instruction or taking the thread off the CPU if the variable does not update before the timeout, see [0049]
US 2003/0023658 teaches an instruction streaming buffer that includes thread switching logic that implements a thread interleaving or switching scheme, see [0056] and Figs. 5-6.
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183