DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 05/19/2026 regarding the prior art rejections of Claims 1 - 27 have been fully considered not are not persuasive.
The Remarks argue that:
As an initial matter, independent Claims 1, 8 and 19 are directed to devices and a method or analyzing a fault in a memory device by (1) accumulating error information from the memory device and (2) reflecting device information including architectural information and data input/output information onto the accumulated error information. Independent Claims 1, 8 and 19 feature (emphasis added)
- Claim 1: "a fault analysis device configured to analyze a fault of the memory device by accumulating an error information from the memory device and reflecting device information, including architectural information on the plurality of cell blocks and data input/output information, onto the accumulated error information";
Richter does not disclose, teach or suggest the features identified above.
Due to the lack of disclosure in Richter, the Office Action relies solely on the Uhde document for the features identified above.
The Examiner agrees and argues “architectural information and data input/output information,” is too broad of a claim and is open to interpretation as the claim refers to it as part of the “error information from the memory device.” The remarks refer to figures but don’t differentiate from the prior art with claim language. In addition, in the previous office action the examiner submits Uhde teaches the limitations of “architectural information and data input/output information,” and not Richter. Richter teaches methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. Uhde teaches “to simplify and/or improve error monitoring in a control and data transmission system for redundant process control, provided is a method for error monitoring in which errors detected by a first control device are stored locally as well as transmitted to at least one redundant second control device, which is arranged remotely, and also stored there so that in each case the error history of both control devices and is available locally for diagnosing the whole redundant system.” (Abstract) In combination, one skilled in the art can use Richter and Udhe to conclude the claimed limitations of the presented application, maintaining the previous prior art rejection.
Claims 2 – 7 which depend from amended claim 1, have been considered and rejected.
Claims 9 - 18 which depend from amended claim 8, have been considered and rejected.
Claim 20 - 27 which depends from claim 19, has been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 27 are rejected under 35 U.S.C. 103 as being unpatentable over Richter (US 2020/0201718 A1) in view of Uhde (US 2016/0154693 A1).
In regards to claim 1, Richter teaches:
A memory system, comprising: at least one memory device including a plurality of cell blocks, word line drivers, and bit line sense amplifiers, wherein the plurality of cell blocks are (0024 & 0035 - 0036, The host device may include a plurality of drivers and a plurality of channels linking the host device with the memory device. This may include output driver circuitry and various other circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to carry out the functions described herein. A memory array 170 may be a collection (e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data.) disposed along a first direction and a second direction, and each of the plurality of cell blocks (0022, The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device 110.) is configured to share the word line drivers with adjacent cell blocks in the first direction, to share bit line sense amplifiers with adjacent cell blocks in the second direction, (0024 & 0072, The host device may include a plurality of drivers and a plurality of channels linking the host device with the memory device. the sense component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205.) and to input/output data through a plurality of data pads; (0176, a controller located at a memory device that support reporting control information errors)
Richter fails to teach:
and a fault analysis device configured to analyze a fault of the memory device by accumulating an error information from the memory device and reflecting device information, including architectural information on the plurality of cell blocks and data input/output information, onto the accumulated error information.
However, Uhde teaches:
and a fault analysis device configured to analyze a fault of the memory device by accumulating an error information from the memory device and reflecting device information, including architectural information on the plurality of cell blocks and data input/output information, onto the accumulated error information. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 2, Richter in view of Uhde teaches the memory system of claim 1.
Richter fails to teach:
wherein the architectural information includes: one or more selected from a layout of word lines and bit lines of each cell block, a layout of redundancy word lines and bit lines of each cell block, a number of memory cells arranged per word line, a number of bit lines specified by one column address, a layout of bit line sense amplifiers of each cell block, and a layout of word line drivers of each cell block.
However, Uhde teaches:
wherein the architectural information includes: one or more selected from a layout of word lines and bit lines of each cell block, a layout of redundancy word lines and bit lines of each cell block, a number of memory cells arranged per word line, a number of bit lines specified by one column address, a layout of bit line sense amplifiers of each cell block, and a layout of word line drivers of each cell block. (0040, overall redundancy-related diagnosis of the redundant system 10, the control devices 100 and 200 are therefore designed to transmit pending error information to the respective partner controller so that this error information is available and can be displayed in a suitable manner on both sides, on the part of the respective local control device and on the part of the control device remote therefrom.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 3, Richter in view of Uhde teaches the memory system of claim 1.
Richter fails to teach:
wherein the data input/output information includes: a mapping information between the plurality of data pads and the plurality of cell blocks according to a data width option and a burst length.
However, Uhde teaches:
wherein the data input/output information includes: a mapping information between the plurality of data pads and the plurality of cell blocks according to a data width option and a burst length. (0037, Redundancy control logic 32 thus receives the column address portion of the memory address and, if a redundant cell is to replace a cell in memory array 20, maps that column address to the physical address of the appropriate redundant column 25.sub.0, 25.sub.1, and applies that mapped physical address to column decoder 28 on lines CA_MAP.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 4, Richter in view of Uhde teaches the memory system of claim 3:
wherein the mapping information includes: one or more selected from a data pad (DQ) aligned structure in which data output from one cell block are output through one corresponding data pad during the burst length, a burst length (BL) aligned structure in which data output from one cell block are output through all data pads during one or more unit bursts of the burst length, and a mixed aligned structure of the DQ aligned structure and the BL aligned structure. (0054, The quantity of memory cells to be read in response to a read command may be referred to as the read burst length.)
With regards to claim 5, Richter in view of Uhde teaches the memory system of claim 1:
wherein the memory device includes a plurality of banks, each of the plurality of banks is the plurality of cell blocks. (0198 - 0200, At block 1105; At block 1110; At block 1120;)
With regards to claim 6, Richter in view of Uhde teaches the memory system of claim 1:
wherein the fault analysis device is configured to: check error locations of data output from the plurality of cell blocks based on the accumulated error information, configure a physical layout of the plurality of cell blocks based on the architectural information to identify bad cell blocks including the error locations, and analyze faults of the bad cell blocks according to the data input/output information. (0016, The control information included in control signaling may include commands, addresses, or error detection/correction information, or a combination thereof. In some cases, errors—e.g., due to transmission, reception, signal lane, and/or timing errors—may be detected in control information.)
With regards to claim 7, Richter in view of Uhde teaches the memory system of claim 1:
wherein, based on information on the analyzed fault, the fault analysis device instructs the memory device to perform a post package repair operation, or requests an error correction operation, a page offlining operation, a row remap operation, a bank sparing/migration operation, or an unuse of the memory device to a host. (0016, The control information included in control signaling may include commands, addresses, or error detection/correction information, or a combination thereof. In some cases, errors—e.g., due to transmission, reception, signal lane, and/or timing errors—may be detected in control information.)
In regards to claim 8, Richter teaches:
A fault analysis device, comprising: a memory fault analyzer configured to analyze a fault of a memory device by accumulating an error information from the memory device and reflecting device information including architectural information on a plurality of cell blocks and data input/output information, onto the accumulated error information, the memory device including the plurality of cell blocks, word line drivers, and bit line sense amplifiers, (0024 & 0035 - 0036, The host device may include a plurality of drivers and a plurality of channels linking the host device with the memory device. This may include output driver circuitry and various other circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to carry out the functions described herein. A memory array 170 may be a collection (e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data.) wherein the plurality of cell blocks are disposed along a first direction and a second direction, and each of the plurality of cell blocks is configured to (0022 & 0034, The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device 110.The output device 150 may represent a device or signal external to the system 100 configured to receive an output from the system 100 or any of its components.) share the word line drivers with adjacent cell blocks in the first direction to share the bit line sense amplifiers with adjacent cell blocks in the second direction, and to input/output data of through a plurality of data pads; (0024 & 0072, The host device may include a plurality of drivers and a plurality of channels linking the host device with the memory device. the sense component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205.)
Richter fails to teach:
and a reliability, accessibility, and serviceability (RAS) manager configured to perform an operation of improving a reliability of the memory device based on information on the analyzed fault.
However, Uhde teaches:
and a reliability, accessibility, and serviceability (RAS) manager configured to perform an operation of improving a reliability of the memory device based on information on the analyzed fault. (Abstract, To simplify and/or improve error monitoring in a control and data transmission system for redundant process control;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 9, Richter in view of Uhde teaches the fault analysis device of claim 8:
further comprising: an information storage configured to store the device information in advance, and receive unique product information from the memory device during boot-up to extract a corresponding device information based on the unique product information. (0034, The output device 150 may represent a device or signal external to the system 100 configured to receive an output from the system 100 or any of its components.)
With regards to claim 10, Richter in view of Uhde teaches the fault analysis device of claim 8:
wherein the memory fault analyzer is configured to: check error locations of data output from the plurality of cell blocks based on the accumulated error information, configure a physical layout of the plurality of cell blocks based on the architectural information to identify bad cell blocks including the error locations, and analyze faults of the bad cell blocks according to the data input/output information and generate a fault information. (0016, The control information included in control signaling may include commands, addresses, or error detection/correction information, or a combination thereof. In some cases, errors—e.g., due to transmission, reception, signal lane, and/or timing errors—may be detected in control information.)
With regards to claim 11, Richter in view of Uhde teaches the fault analysis device of claim 10:
wherein, when errors are located in a single column address and a single row address in the physical layout, the memory fault analyzer generates the fault information notifying a single-bit error. (0025, a memory device 110 may be an independent device or component that is configured to be in communication with other components of the system 100 and provide physical memory addresses/space to potentially be used or referenced by the system 100.)
With regards to claim 12, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
when errors are located in a single column address of one or two adjacent cell blocks in the second direction in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a bit line or bit line sense amplifier corresponding to the single column address.
However, Uhde teaches:
when errors are located in a single column address of one or two adjacent cell blocks in the second direction in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a bit line or bit line sense amplifier corresponding to the single column address. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 13, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
wherein, when errors are located in a single row address of one or two adjacent cell blocks in the first direction in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a word line or word line driver corresponding to the single row address.
However, Uhde teaches:
wherein, when errors are located in a single row address of one or two adjacent cell blocks in the first direction in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a word line or word line driver corresponding to the single row address. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 14, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
wherein, when errors occur in consecutive row addresses equal to or less than a predetermined number of a single cell block in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a main word line corresponding to the consecutive row addresses.
However, Uhde teaches:
wherein, when errors occur in consecutive row addresses equal to or less than a predetermined number of a single cell block in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a main word line corresponding to the consecutive row addresses(0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 15, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
wherein, when errors are located in the same order of word lines disposed in two adjacent main word lines in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a contact shared by word line drivers for driving the same order of the word lines.
However, Uhde teaches:
wherein, when errors are located in the same order of word lines disposed in two adjacent main word lines in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a contact shared by word line drivers for driving the same order of the word lines. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 16, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
wherein, when errors are located in the same order of word lines for each of a plurality of main word lines in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a signal path commonly provided to word line drivers for driving the same order of the word lines.
However, Uhde teaches:
wherein, when errors are located in the same order of word lines for each of a plurality of main word lines in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a signal path commonly provided to word line drivers for driving the same order of the word lines. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 17, Richter in view of Uhde teaches the fault analysis device of claim 10.
Richter fails to teach:
wherein, when data including errors are input/output through one data pad in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a data pad and a data path related thereto.
However, Uhde teaches:
wherein, when data including errors are input/output through one data pad in the physical layout, the memory fault analyzer generates the fault information notifying a fault in a data pad and a data path related thereto. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 18, Richter in view of Uhde teaches the fault analysis device of claim 8:
wherein, based on information on the analyzed fault, the RAS manager instructs the memory device to perform a post package repair operation, or requests an error correction operation, a page offlining operation, a row remap operation, a bank sparing/migration operation, or an unuse of the memory device to a host. (0153, the control information may also include error detection/correction information (e.g., parity and/or cyclic redundancy check (CRC) bits) that enable a receiving device to detect and/or repair errors in received control information.)
In regards to claim 19, Richter teaches:
A fault analysis method, comprising: accumulating an error information from at least one memory device including a plurality of cell blocks, word line drivers, and bit line sense amplifiers, wherein the plurality of cell blocks are disposed along a first direction and a second direction (0024 & 0035 - 0036, The host device may include a plurality of drivers and a plurality of channels linking the host device with the memory device. This may include output driver circuitry and various other circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to carry out the functions described herein. A memory array 170 may be a collection (e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data.) and each of the plurality of cell blocks is configured to share the word line drivers with adjacent cell blocks in the first direction to share the bit line sense amplifiers with adjacent cell blocks in the second direction, and to input/output data through a plurality of data pads; (0072 & 0176, the sense component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205.a controller located at a memory device that support reporting control information errors.)
Richter fails to teach:
checking error locations of data output from the plurality of cell blocks based on the accumulated error information; configuring a physical layout of the plurality of cell blocks based on architectural information of the plurality of cell blocks; and identifying bad cell blocks including the error locations from the physical layout, and generating a fault information on the bad cell blocks according to data input/output information.
However, Uhde teaches:
checking error locations of data output from the plurality of cell blocks based on the accumulated error information; configuring a physical layout of the plurality of cell blocks based on architectural information of the plurality of cell blocks; and identifying bad cell blocks including the error locations from the physical layout, and generating a fault information on the bad cell blocks according to data input/output information. (0038, For error diagnosis, error messages which have accumulated in one of the control devices 100 and 200 respectively can be displayed in the form of error codes as well as in plain text on the particular display 150 and 250 respectively. Advantageously, the accumulated error information is stored in the history and displayed in lists;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a memory system including drivers, sense amplifiers, and cell blocks of Richter with the teaching of Uhde, which teaches memory fault analysis in order to manage and improve errors in the memory. (Uhde: 0038, in order to give an overview of the system function directly at the device.)
With regards to claim 20, Richter in view of Uhde teaches the fault analysis method of claim 19:
further comprising: storing device information in advance, and receiving unique product information from the memory device during boot-up to extract the architectural information and the data input/output information based on the unique product information. (0025, a memory device 110 may be an independent device or component that is configured to be in communication with other components of the system 100 and provide physical memory addresses/space to potentially be used or referenced by the system 100.)
With regards to claim 21, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 11 as analyzed accordingly.
With regards to claim 22, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 12 as analyzed accordingly.
With regards to claim 23, Richter in view of Uhde teaches fault analysis method of claim 19 and corresponds to claim 13 as analyzed accordingly.
With regards to claim 24, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 14 as analyzed accordingly.
With regards to claim 25, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 15 as analyzed accordingly.
With regards to claim 26, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 16 as analyzed accordingly.
With regards to claim 27, Richter in view of Uhde teaches the fault analysis method of claim 19 and corresponds to claim 17 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Kim (US 2022/0334905 A1): A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.
Waseda (US 2016/0266825 A1): According to one embodiment, a memory system includes a nonvolatile memory including a first storage area; and a memory controller which receives first data from a host device to access the nonvolatile memory, and causes the first storage area to store therein log data based on the first data.
Conclusion
Applicant's arguments filed 05/19/2026 regarding the prior art rejections of Claims 1 – 27 have
been fully considered but are not persuasive.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 7/29/2026
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