DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-21 are presented for examination.
Response to Arguments
3. Applicant’s argument filed on 05/27/2026 with respect claims 1-21 have been fully considered but they are not persuasive.
The applicant contends that the Bains does teach or suggest how such device specific commands are generated and provided to the memory devices. See the applicant’s remark pages 11-12.
Examiner respectfully disagrees and asserts the Bains et al. (US 2024/0211344 A1) in paragraphs [0191]- [0192], and Fig. 1 teaches the such limitation. For example, system 1400 illustrates one example of a system with memory devices that share a control bus (C/A (command/address) bus 1442) and a data bus (data bus 1446), which are illustrated as split into two parts for Channel 0 (CH[0]) and Channel 1 (CH[1]). The memory devices are represented as DRAM (dynamic random access memory) devices 1430. In one example, the two separate channels share C/A bus 1442 connection between controller 1440 to RCD 1420. In one example, the separate channels will have separate C/A buses. DRAM devices 1430 can be individually accessed with device specific commands, and can be accessed in parallel with parallel commands. See paragraph [0191].
RCD (registered clock driver or registering clock driver) 1420 represents a controller for DIMM (dual inline memory module) 1410. In one example, RCD 1420 receives information from controller 1440 and buffers the signals to the various DRAM devices 1430. By buffering the input signals from controller 1440, the controller only sees the load of RCD 1420, which can then control the timing and signaling to DRAM devices 1430. See paragraph [0192]. Also see Fig. 1 printed below for your convenience.
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Also, the applicant contends that the Bains reference is silent on a start address and an end address that defines an exclusion area with target data that is not to be corrected. See the applicant’s remark page 11.
The Examiner respectfully disagrees and asserts the Bains et al. (US 2024/0211344 A1) in paragraphs [0033], [0111], [0104], [0121] [0131], [0149], [0126], and Fig. 9 teaches the such feature. For example, in one example, the host can provide an indication to the on-memory error scrubbing engine of rows of memory that have been offlined by the host. For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host. See paragraph [0033].
In one example, address generation logic 620 receives as an input an ECS mode check 612, which represents the ECS mode configured for the ECS logic to execute. For example, one mode may indicate that error scrubbing should be skipped for excluded addresses. In another example, another mode may indicate that error scrubbing should be performed for excluded addresses, but the result should be excluded from counting. See paragraph [0104].
In one example, system 700 includes a storage unit within the ECS counter logic to store offlined or excluded addresses. In one example, system 700 implements one or more protocols to transfer and manage offlined page addresses between the memory controller and the memory device. In one example, system 700 implements one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller. See paragraph [0111].
In either option, the memory can be said to skip the scrub count for the excluded address. In one example, the memory controller provides the excluded address information to the memory device to excluded from the ECS count with a special configuration command. In one example, excluded address memory 732 is writeable by the memory controller, such as by a mode register write command or multipurpose register write command. In one example, the memory controller will set a mode register bit to determine the behavior of the ECS system when an excluded address is encountered, whether to perform error scrubbing and exclude the result, or whether to simple not perform error scrubbing. In one example, memory controller has a command to clear selected addresses from excluded address memory 732. In one example, the memory controller can clear the entire excluded address memory 732 with a single command. See paragraph [0121].
Memory controller 920 can pass the hints to memory device 920, which receives the hints at controller 922. Controller 922 represents an on-memory controller that controls the operations internal to memory device 920. In one example, controller 922 applies range control (CTRL) 924 to the received hints. Range control 924 represents default configuration or protocol settings by which controller 922 can interpret the hints provided by memory controller 910. In one example, the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses. In one example, the hints are individual addresses, which range control 924 can interpret as an address range, by including a default range to the address. See paragraph [0131].
In one example, system 1000 includes address ranges to associate with the various hints 1010, as represented by the queues for the different hints. Queues[N−1:0] can provide start address and end address registers for each hint, thus providing regions of addresses for hints. See paragraph [0131]. For the Applicant’s convenience, see Fig. 9 is reproduced below.
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As described above and shown in Figs 1 and 9, it would have been obvious to one of ordinary skill in the art that Bains teaches or suggests specific commands [command/address (C/A)] are independently generated and provided to the memory devices [DRAM devices 1430 can be individually accessed with device specific commands, and can be accessed in parallel with parallel commands]; and defined an exclusion area with target data [one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller]. Also, the Examiner directs the applicant’s attention that the independent claims are silent on “target data that is not to be corrected.” Emphasis added.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claims 1-21 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Bains et al. (US 2024/0211344 A1) "herein after as Bains" in view of Seo et al. (US 2023/0137339 A1) "herein after as Seo."
As per claim 1:
Bains substantially teaches or discloses a memory system (see paragraph [0057], herein system 200 represents components of a memory subsystem; Fig. 2, system 200; and Fig. 14, system 1400), comprising: a plurality of memory devices (see paragraph [0058], herein memory module 250 represents a module that includes multiple memory devices 260 ; Fig. 2, memory decides 206; and Fig. 14, DRAMs 1430) each including a memory cell (see paragraph [0059], herein Array 262 represents memory cells within memory device 26, and Fig. 2 array 262) region and an error correction circuit (see paragraph [0059], herein memory device 260 includes ECC 272 to perform error checking and correction within memory device 260; and Fig. 14 ECC 1432); and a memory controller configured to independently generate and provide [signal] to each of the plurality of memory devices (see paragraph [0048], herein Memory controller 320 manages system wide ECC, and can detect and correct errors across multiple different memory resources in parallel (e.g., multiple devices of memory 330); paragraph [0191]; herein DRAM devices 1430 can be individually accessed with device specific commands, and can be accessed in parallel with parallel commands; paragraph [0192], herein RCD 1420 receives information from controller 1440 and buffers the signals to the various DRAM devices 1430. By buffering the input signals from controller 1440, the controller only sees the load of RCD 1420, which can then control the timing and signaling to DRAM devices 143, and Fig. 14), wherein, during a read operation, each of the plurality of memory devices defines an exclusion area between a start address and an end address (see paragraph [0111], herein system 700 implements one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller; and paragraph [0131], herein Range control 924 represents default configuration or protocol settings by which controller 922 can interpret the hints provided by memory controller 910. In one example, the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses. In one example, the hints are individual addresses, which range control 924 can interpret as an address range, by including a default range to the address), which are included in the provided off address (see paragraph [0194], herein C/A bus 1422[0] AND C/A bus 1422[1] (collectively, C/A buses 1422) are typically unilateral buses or unidirectional buses to carry command and address information from controller 1440 to DRAM devices 1430), and controls the error correction circuit to selectively perform an error correction operation on a target area by checking whether the target area is included in the exclusion area in the memory cell region [ ] (see paragraph [0033], herein For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host; paragraph [0121], herein the memory controller will set a mode register bit to determine the behavior of the ECS system when an excluded address is encountered, whether to perform error scrubbing and exclude the result, or whether to simple not perform error scrubbing; and paragraphs [0044], [0059], & [0212]).
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Bains does not explicitly teach an off mode signal and an off address. However, Seo in the same the field of endeavor teaches off mode signal and an off address (see abstract, paragraph [0030], herein According to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data., and Fig. 1.
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by including an off mode signal and an off address. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the off mode signal and an off address would have improved the memory system performance.
As per claim 2:
Seo teaches that wherein the memory controller independently generates and provides the off mode signal and the off address to each of the plurality of memory devices along with a mode setting command (see paragraph [0030], herein the uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data).
As per claim 3:
Seo teaches that wherein the memory controller independently generates and provides the off address to each of plurality of memory devices along with a mode setting command (see paragraph [0030], herein the uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data), and wherein the memory controller further provides an off command for setting the off mode signal to each of the plurality of memory devices (see paragraph [0030], herein the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100).
As per claim 4:
Bains teaches that wherein each of the plurality of memory devices omits the error correction operation on data when the target area with the data is included in the exclusion area, and performs the error correction operation on data when the target area with the data is not included in the exclusion area (see abstract; paragraph [0033], herein For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host).
As per claim 5:
Bains teaches that wherein, for each of the plurality of memory devices, the memory controller collects an address of an area where an error has occurred beyond an error correction capability (see paragraph [0035], abstract; herein in response to detection of a multibit error (MBE), the system can determine whether the MBE is part of a pattern of errors related to a specific address of the memory. When detected errors indicate a pattern of errors, the host can trigger a row hammer response related to the specific address).
Bains does not explicitly teach generates the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses.
However, Seo in the same the field of endeavor teaches generates the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses (see abstract, paragraph [0030], herein according to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data., and Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by generating the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses would have improved the memory system performance.
As per claim 6:
Bains substantially teaches or discloses plurality of memory devices, each memory device comprising (see Fig. 2 , memory devices 260; and Fig. 14 DRAM 1430): a memory cell region (see paragraph [0059], herein array 262 represents memory cells within memory device 260, and Fig. 2 array 262); an error correction circuit (see Fig. 2 ECC 272; and Fig. 14 ECC 1432) configured to define an exclusion area between a start address and an end address, which are included in the off address (see paragraph [0111], herein system 700 implements one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller; and paragraph [0131], herein Range control 924 represents default configuration or protocol settings by which controller 922 can interpret the hints provided by memory controller 910. In one example, the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses. In one example, the hints are individual addresses, which range control 924 can interpret as an address range, by including a default range to the address), and generate the correction off signal by checking whether the target area is included in the exclusion area [ ] (see paragraph [0033], herein For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host; paragraph [0121], herein the memory controller will set a mode register bit to determine the behavior of the ECS system when an excluded address is encountered, whether to perform error scrubbing and exclude the result, or whether to simple not perform error scrubbing; and paragraphs [0044], [0059], & [0212]), wherein the off address is independently generated for each of the plurality of memory devices (see paragraph [0048], herein Memory controller 320 manages system wide ECC, and can detect and correct errors across multiple different memory resources in parallel (e.g., multiple devices of memory 330); paragraph [0191]; herein DRAM devices 1430 can be individually accessed with device specific commands, and can be accessed in parallel with parallel commands; paragraph [0192], herein RCD 1420 receives information from controller 1440 and buffers the signals to the various DRAM devices 1430. By buffering the input signals from controller 1440, the controller only sees the load of RCD 1420, which can then control the timing and signaling to DRAM devices 143, and Fig. 14).
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Bains does not explicitly teach a mode setting circuit configured to store a preliminary off mode signal and an off address according to a mode setting command. However, Seo in the same the field of endeavor teaches a mode setting circuit configured to store a preliminary off mode signal and an off address according to a mode setting command (see abstract, paragraph [0041], herein the CMD DEC 1130 may generate one or more internal control signals for driving the data chip 20 by decoding the command CMD input from outside of the memory device 100 (e.g., from the memory controller 200 of FIG. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by a mode storing a preliminary off mode signal and an off address according to a mode setting command. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the storing a preliminary off mode signal and an off address according to a mode setting command improved the memory system performance.
As per claim 7:
Bains teaches that wherein the mode setting command and the off command are provided from a memory controller (see paragraph [0070], herein Manual ECS mode can refer to a mode in which ECS operations are managed by memory controller 210, where memory controller 210 is responsible for sending ECS commands to memory device 260).
As per claim 8:
Bains teaches that wherein the error correction control circuit includes (see Fig. 2, ESC 270): an area comparison circuit configured to activate the correction off signal when a row address input during the read operation is included between the start address and an end address, [ ] (see paragraph [0298], herein the identified address comprises a specific row address requested by the host for the performance of ECS operations. In one example, the error scrubbing logic is to perform ECS operations on the specific row address requested by the host and rows with consecutive addresses to the specific row address.; and paragraph [0131], herein the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses).
Bains does not explicitly teach a mode control circuit configured to generate an off mode signal according to the off command or the preliminary off mode signal.
However, Seo in the same the field of endeavor teaches a mode control circuit configured to generate an off mode signal according to the off command or the preliminary off mode signal (see abstract, paragraph [0082], herein as an uncorrected read command NECC_CMD is received from a memory controller, a CMD DEC 610 may generate a control signal that inactivates some operations of the ECC engine 620, for example, at least one of first to third control signals CTRL1, CTRL2, and CTRL3, and Fig. 8, component 610). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by generating an off mode signal according to the off command or the preliminary off mode signal. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating an off mode signal according to the off command or the preliminary off mode signal would have improved the memory system performance.
As per claim 9:
Bains teaches that an output circuit configured to output an error correction code read from the target area through a separate pad according to the correction off signal, during the read operation (see paragraph [0048], herein system 100 includes ECC logic 130 to perform error checking and correction operations on selected or addressed memory location(s). In one example, ECC logic 130 generates an output flag (ERROR DETECT) when an error is detected in a memory location).
As per claim 10:
Bains teaches that an error correction code generation circuit configured to generate an error correction code using write data during a write operation, wherein the memory cell region stores the write data and the error correction code (see paragraph [0044], herein when the memory controller provides some address information, the selection logic of system 100 can be selectively more complex. Based on internal address information or external address information, system 100 can check all code words and check bits within the memory. More specifically, system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses).
As per claim 11:
Bains substantially teaches or discloses an operating method of a plurality of memory devices (see Fig. 2, memory devices 260; and Fig. 14 DRAM 1430), comprising: receiving a read command for a target area in a memory cell region (see paragraph [0044], herein system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses. In one example, the ECS system can read the memory array, correct errors with internal ECC (error checking and correction) logic, and write back corrected data. In one example, the ECS system can read the memory array and write the data back to the array every time, whether or not the ECC detected and corrected an error); defining an exclusion area between a start address and an end address which are included in the off address (see paragraph [0111], herein system 700 implements one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller; and paragraph [0131], herein Range control 924 represents default configuration or protocol settings by which controller 922 can interpret the hints provided by memory controller 910. In one example, the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses. In one example, the hints are individual addresses, which range control 924 can interpret as an address range, by including a default range to the address); checking whether the target area is included in an exclusion area [ ] (see paragraph [0044], herein when the memory controller provides some address information, the selection logic of system 100 can be selectively more complex. Based on internal address information or external address information, system 100 can check all code words and check bits within the memory. More specifically, system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses); and selectively performing an error correction operation on data read from the target area according to the checking result (see paragraph [0048], herein system 100 includes ECC logic 130 to perform error checking and correction operations on selected or addressed memory location(s); and paragraph [0059], herein memory controller 210 includes error control 220, which represents logic or circuitry within memory controller 210 to perform error correction on data received from memory devices 260. Memory device 260 includes ECC 272 to perform error checking and correction within memory device 260. ECC 272 can be referred to as on-device or on-die ECC for the memory device, which is distinct from error correction 222 of memory controller 210. ECC 272 can operate locally on the data stored within array 262. Array 262 represents memory cells within memory device 260. Array 262 can include multiple rows of memory; and paragraph [0212]).
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Bains does not explicitly teach storing a preliminary off mode signal and an off address in a mode setting circuit according to a mode setting command; independently generating an off mode signal according to an off command or the stored preliminary off mode signal for each of the plurality of memory devices. However, Seo in the same the field of endeavor teaches storing a preliminary off mode signal and an off address in a mode setting circuit according to a mode setting command (see abstract, paragraph [0041], herein the CMD DEC 1130 may generate one or more internal control signals for driving the data chip 20 by decoding the command CMD input from outside of the memory device 100 (e.g., from the memory controller 200 of FIG. 1); independently generating an off mode signal according to an off command or the stored preliminary off mode signal for each of the plurality of memory devices (see, abstract, paragraph [0030], herein According to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data, and Fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by including storing a preliminary off mode signal and an off address in a mode setting circuit according to a mode setting command; independently generating an off mode signal according to an off command or the stored preliminary off mode signal for each of the plurality of memory devices. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the storing a preliminary off mode signal and an off address in a mode setting circuit according to a mode setting command; independently generating an off mode signal according to an off command or the stored preliminary off mode signal for each of the plurality of memory devices would have improved the memory system performance.
As per claim 12:
Bains teaches that wherein the checking whether the target area is included in the exclusion area includes: comparing a row address designating the target area with a start address and the end address (see paragraph [0116], herein address control 720 generates internal address information, shown as one of the inputs to compare 730. Compare 730 represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare 730 is excluded address memory 732. In one example, compare 730 compares the address generated by address control 720 to all entries in excluded address memory 732); and determining that the target area is included in the exclusion area when the row address is included between the start address and the end address (see paragraph [0298], herein the identified address comprises a specific row address requested by the host for the performance of ECS operations. In one example, the error scrubbing logic is to perform ECS operations on the specific row address requested by the host and rows with consecutive addresses to the specific row address.; and paragraph [0131], herein the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses).
As per claim 13:
Bains teaches that wherein the selectively performing the error correction operation includes: omitting the error correction operation on the data read from the target area when the target area is included in the exclusion area (see abstract; paragraph [0033], herein For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host).
As per claim 14:
Bains teaches that outputting the read data on which the error correction operation is omitted through a data pad (see paragraph [0048], herein ECC logic 130 generates the flag in response to detecting a multibit error (MBE)), and outputting an error correction code read from the target area through a separate pad (see paragraph [0048], herein ECC logic 130 generates an output flag (ERROR DETECT) when an error is detected in a memory location).
As per claim 15:
Bains teaches that providing the mode setting command and the off command from a memory controller (see paragraph [0070], herein Manual ECS mode can refer to a mode in which ECS operations are managed by memory controller 210, where memory controller 210 is responsible for sending ECS commands to memory device 260).
As per claim 16:
Bains substantially teaches or discloses an operating method of a memory system, comprising see paragraph [0057], herein system 200 represents components of a memory subsystem; Fig. 2, system 200; and Fig. 14, system 1400): providing, at a memory controller, [signal] area to at least one selected memory device among a plurality of memory devices (see paragraph [0070], herein Manual ECS mode can refer to a mode in which ECS operations are managed by memory controller 210, where memory controller 210 is responsible for sending ECS commands to memory device 260; paragraph [0191]; herein DRAM devices 1430 can be individually accessed with device specific commands, and can be accessed in parallel with parallel commands; paragraph [0192], herein RCD 1420 receives information from controller 1440 and buffers the signals to the various DRAM devices 1430. By buffering the input signals from controller 1440, the controller only sees the load of RCD 1420, which can then control the timing and signaling to DRAM devices 143, and Fig. 14); providing, at the memory controller, a read command for a target area to the plurality of memory devices (see paragraph [0174], herein Memory controller 1310 includes command logic 1314 to generate commands for memory device 1320. Commands can include commands such as Write commands or Read commands; and paragraph [0192]); defining an exclusion area between a start address and an end address which are included in the off address (see paragraph [0111], herein system 700 implements one or more protocols to manage the scrubbing of offlined pages and the exclusion of offlined pages from error count information provided by the ECS system to the memory controller; and paragraph [0131], herein Range control 924 represents default configuration or protocol settings by which controller 922 can interpret the hints provided by memory controller 910. In one example, the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses. In one example, the hints are individual addresses, which range control 924 can interpret as an address range, by including a default range to the address), at the selected memory device, and checking whether the target area is included in the exclusion area [ ] (see paragraph [0044], herein when the memory controller provides some address information, the selection logic of system 100 can be selectively more complex. Based on internal address information or external address information, system 100 can check all code words and check bits within the memory. More specifically, system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses; and paragraph [0121], herein the memory controller will set a mode register bit to determine the behavior of the ECS system when an excluded address is encountered, whether to perform error scrubbing and exclude the result, or whether to simple not perform error scrubbing); and selectively performing, at the selected memory device, an error correction operation on data read from the target area according to the checking result (see paragraph [0048], herein system 100 includes ECC logic 130 to perform error checking and correction operations on selected or addressed memory location(s); and paragraph [0059], herein memory controller 210 includes error control 220, which represents logic or circuitry within memory controller 210 to perform error correction on data received from memory devices 260. Memory device 260 includes ECC 272 to perform error checking and correction within memory device 260. ECC 272 can be referred to as on-device or on-die ECC for the memory device, which is distinct from error correction 222 of memory controller 210. ECC 272 can operate locally on the data stored within array 262. Array 262 represents memory cells within memory device 260. Array 262 can include multiple rows of memory, and paragraph [02121]).
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Bains does not explicitly teach an off mode signal and an off address; storing the off mode signal and the off address, at the selected memory device; wherein the off mode signal and the off address are independently generated for each of the plurality of memory devices. However, Seo in the same the field of endeavor teaches off mode signal and an off address (see abstract, paragraph [0030], herein According to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data., and Fig. 1; wherein the off mode signal and the off address are independently generated for each of the plurality of memory devices (see, abstract, paragraph [0030], herein According to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data, and Fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by including an off mode signal and an off address; storing the off mode signal and the off address; and the off mode signal and the off address are independently generated for each of the plurality of memory devices. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the off mode signal and an off address; storing the off mode signal and the off address, and the off mode signal and the off address are independently generated for each of the plurality of memory devices would have improved the memory system performance.
As per claim 17:
Bains teaches that wherein the memory controller provides the [signal] to the selected memory device, along with a mode setting command (see paragraph [0174], herein Memory controller 1310 includes command logic 1314 to generate commands for memory device 1320. Commands can include commands such as Write commands or Read commands. Commands can also include Activate commands, Precharge commands, Refresh commands, or other commands. In one example, memory controller 1310 includes refresh logic 1372, which represents logic to control the refreshing of memory device 1320).
Bains does not explicitly teach an off mode signal and the off address. However, Seo in the same the field of endeavor teaches off mode signal and the off address (see abstract, paragraph [0030], herein According to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data., and Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by including an off mode signal and an off address. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the off mode signal and an off address would have improved the memory system performance.
As per claim 18:
Seo teaches that wherein the memory controller provides the off address to the selected memory device along with a mode setting command (see paragraph [0030], herein the uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data), and wherein the memory controller further provides an off command for setting the off mode signal to the selected memory device (see paragraph [0030], herein the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100).
As per claim 19:
Bains teaches that wherein the checking whether the target area is included in the exclusion area includes: defining the exclusion area according to the off address (see paragraph [0044], herein based on internal address information or external address information, system 100 can check all code words and check bits within the memory. More specifically, system 100 can perform ECS operations, which include ECC operations to read, correct, and write back memory locations for all selected or specified addresses); comparing a row address designating the target area with the start address and an end address (see paragraph [0116], herein address control 720 generates internal address information, shown as one of the inputs to compare 730. Compare 730 represents an address comparator, or a comparison mechanism to compare generated addresses with addresses identified by the host as offline. The other input to compare 730 is excluded address memory 732. In one example, compare 730 compares the address generated by address control 720 to all entries in excluded address memory 732); and determining that the target area is included in the exclusion area when the row address is included between the start address and the end address (see paragraph [0298], herein the identified address comprises a specific row address requested by the host for the performance of ECS operations. In one example, the error scrubbing logic is to perform ECS operations on the specific row address requested by the host and rows with consecutive addresses to the specific row address.; and paragraph [0131], herein the hints are addresses, which can include start and end addresses, identified by range control 924 to be ranges of addresses).
As per claim 20:
Bains teaches that omitting the error correction operation on the read data at the selected memory device, while performing an error correction operation on the read data at each of unselected memory devices, when the target area is included in the exclusion area (see abstract; paragraph [0033], herein For an error scrubbing engine with ECS logic with transparency that counts and reports on errors detected, the indication of the offlined errors can enable the error scrubbing engine to skip the offlined rows in ECS operation counts. The skipping can be through not performing the error scrubbing for the offlined pages, or through performing the error scrubbing on the offlined pages but then not including the offlined pages in the error count information provided to the host).
As per claim 21:
Bains teaches that collecting, at the memory controller, an address of an area where an error has occurred beyond an error correction capability of each of the plurality of memory devices (see paragraph [0035], abstract; herein in response to detection of a multibit error (MBE), the system can determine whether the MBE is part of a pattern of errors related to a specific address of the memory. When detected errors indicate a pattern of errors, the host can trigger a row hammer response related to the specific address). Bains does not explicitly teach generating the off mode signal and the off address for each of the plurality of memory devices based on collected addresses.
However, Seo in the same the field of endeavor teaches generating the off mode signal and the off address for each of the plurality of memory devices based on collected addresses (see abstract, paragraph [0030], herein according to an embodiment, the memory controller 200 may transmit a normal read command r_CMD and an uncorrected read command NECC_CMD to the memory device 100. The normal read command r_CMD may be a command for reading corrected data, which may be generated as a result of correcting an error in data through an on-die error correction code (ECC) operation of the memory device 100. The uncorrected read command NECC_CMD may be a command for inactivating the on-die ECC operation from the memory device 100 and reading data., and Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Bains with the teachings of Seo by generating the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the generating the off mode signal and the off address for each of the plurality of memory devices based on the collected addresses would have improved the memory system performance.
Examiner Notes
5. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
6. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
7. THIS ACTION IS MADE FINAL; Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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