DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simadarri Ramadass et al. 2024076740 herein Ramadass in view of Agarwal et al. 20190102326 herein Agarwal.
Per claim 14, Ramadass discloses: a host device; (fig. 1, 150) and a memory expanding device, (fig. 1, 130) wherein the host device comprises: a cache controller (fig. 1, 112) a root complex (fig. 1, 120) and wherein the memory expanding device comprises: a memory device; (fig. 1, 134) and a memory controller (fig. 1, 132).
Ramadas discloses a prefetching but does not specifically: including a prefetch support circuit configured to generate prefetch information; a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device; and one or more prefetch buffers storing the prefetch data, including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device ().
Agarwal discloses: including a prefetch support circuit configured to generate prefetch information; (¶0035; Hardware prefetch engines can help determine patterns and prefetch into a dedicated or a shared cache (mid-level cache or L2 cache or last level cache (LLC) prefetch).) a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device; (¶0040; the root complex to perform certain optimization processes prior to receiving further data packets from the devices 220a-c. Other use cases include caching policy determination (including cache prefetch); the examiner notes that the optimization includes prefetching) and one or more prefetch buffers storing the prefetch data, (fig. 1 ¶0021; re-order buffers in reorder/retirement unit 135, ILTB 120, load/store buffers, and queues may be shared through partitioning) including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device (¶0137; the caching behavior optimization process comprises performing a prefetch of ownership in response to the memory transaction hint indicating a streaming write, performing a prefetch of data and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction, performing a prefetch of ownership and data in response to the memory transaction hint indicating an atomics operation or a cacheable operation).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Ramadass and Agarwal’s memory transaction optimization such as prefetching to improve latency (¶0036).
Claims 1-5 are the device claims corresponding to the systems claims 14-20 and are rejected under the same reasons set forth in connection with the rejection of claims 14-20.
Claim(s) 15, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simadarri Ramadass et al. 2024076740 herein Ramadass and Agarwal et al. 20190102326 herein Agarwal in view of Davis et al. 20060265552 herein Davis.
Per claim 15, the combined teachings of Ramadas and Agarwal discloses a prefetching but does not specifically: wherein the cache controller is configured to search the prefetch buffer for requested data required by the host device, and when the requested data is found in the prefetch buffer, read the requested data from the prefetch buffer.
However, Davis discloses: wherein the cache controller is configured to search the prefetch buffer for requested data required by the host device, and when the requested data is found in the prefetch buffer, read the requested data from the prefetch buffer (fig. 3, ¶0048 and ¶0054; if the requested data is found in a main cache or prefetch cache, then the process continues to step 214, where the requested data is retrieved from the cache and returned for processing at the processor unit 12.When a data block is loaded from a higher level of cache (e.g. L2 or L3) it may be loaded in to lower levels of cache (e.g. L1) as the data block is transferred to the processor. In step 216, if the requested data was found in a prefetch cache, then that prefetch cache data is loaded into the associated main cache (such as the L2 cache)).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Ramadass, Agarwal and Davis prefetching mechanism to improve prefetching. Davis makes processor operation more reliable and efficient (¶0009).
Per claim 16, Davis discloses: wherein the prefetch support circuit is further configured to, when a cache hit occurs, transmit cache hit information and the prefetch information to the memory expanding device through the root complex (fig. 3, 216 and 2325; ¶0048 and ¶0054; if the requested data was found in a prefetch cache, then that prefetch cache data is loaded into the associated main cache (such as the L2 cache), and the prefetch request entry in the prefetch cache is invalidated or discarded. The process is then continues to step 232, described below…. a number of prefetch requests are sent to the prefetch request queue, where that number is based on the prefetch attributes stored in the page table entry associated with the just-issued explicit request along with the number of prefetch requests already pending for this prefetch stream).
Per claim 18, Davis discloses: wherein the prefetch information includes at least one of a Program Counter (PC) and a memory address, (¶0061; The method begins at 302, and in step 304, one prefetch request entry with a count parameter is sent to the prefetch request queue. Step 304 is performed in place of step 232 of FIG. 3.) wherein the prefetch decision circuit is further configured to determine a prefetch address for reading the prefetch data based on the prefetch information and read the prefetch data from the prefetch address of the memory device (¶0054; a number of prefetch requests are sent to the prefetch request queue, where that number is based on the prefetch attributes stored in the page table entry associated with the just-issued explicit request along with the number of prefetch requests already pending for this prefetch stream.).
Claim(s) 17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Simadarri Ramadass et al. 2024076740 herein Ramadass and Agarwal et al. 20190102326 herein Agarwal in view of Levi et al. 20220116473 herein Levi.
Per claim 17, the combined teaching of Ramadass and Agarwal do not specifically disclose: further comprising a switch connecting the host device and the memory expanding device, wherein the prefetch support circuit is further configured to acquire a device latency and a switch level of the memory expanding device while a device enumeration operation is performed, and transmit a transmission latency acquired based on the device latency and a switch latency by the switch level, to the memory expanding device through the root complex.
However, Levi discloses: further comprising a switch connecting the host device and the memory expanding device, (fig. 1) wherein the prefetch support circuit is further configured to acquire a device latency and a switch level of the memory expanding device while a device enumeration operation is performed,(¶0100; NIC processor 212 prefetches data ahead of time from host memory 192 to NIC memory 208. With this implementation, when the data is due to be sent to RX buffer 204 of switch 188, the data is already available locally in NIC memory 208. The latency budget in this embodiment comprises only the following latencies: [0101] ACK latency (A): The latency from the time data (e.g., a message or packet) leaves RX buffer 204, until the switch's flow control mechanism notifies NIC 200 it is ready to receive additional data. [0102] In NIC latency (D): The (relatively small and predictable) latency of accessing NIC memory 208. [0103] Send latency (E): The latency of transferring the data from NIC 200 to RX buffer 204) and transmit a transmission latency acquired based on the device latency and a switch latency by the switch level, to the memory expanding device through the root complex (¶0061; In an embodiment, the prefetch-WQEs specify a time at which NIC processor 56 is to prefetch the sender WQEs and packet data. The prefetch time is typically set to be sufficiently earlier than the transmission time, e.g., earlier by at least the expected worst-case durations of the prefetch transactions, including latencies expected on PCIe bus 36; the examiner interprets the limitation as merely acquiring/using the transmission latency data ).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Ramadass, Agarwal andLevi’s scheduled prefetching to meet a specified prefetching time. Levi improves transmission of packets across network switches with little latency. (¶0024).
Per claim 19, Levi discloses: wherein the prefetch decision circuit includes a time buffer storing request time information when a request is received from the host device ((¶0061; In an embodiment, the prefetch-WQEs specify a time at which NIC processor 56 is to prefetch the sender WQEs and packet data. The prefetch time is typically set to be sufficiently earlier than the transmission time, e.g., earlier by at least the expected worst-case durations of the prefetch transactions, including latencies expected on PCIe bus 36; the examiner interprets the claim as using a specified time).
Per claim 20, Levi discloses: wherein the prefetch decision circuit is further configured to determine a prefetch time point, which is a time point at which the prefetch data is prefetched to the host device, based on the request time information and a transmission latency received from the host device, and prefetch the prefetch data to the host device at the prefetch time point ((¶0061; In an embodiment, the prefetch-WQEs specify a time at which NIC processor 56 is to prefetch the sender WQEs and packet data. The prefetch time is typically set to be sufficiently earlier than the transmission time, e.g., earlier by at least the expected worst-case durations of the prefetch transactions, including latencies expected on PCIe bus 36; the examiner interprets the claim as using a specified time).
Allowable Subject Matter
Claims 6-9 and 12-13 allowed.
Response to Arguments
Applicant's arguments filed 12/31/26 have been fully considered but they are not persuasive.
The applicant argues: Regarding independent claim 1 and 14, Applicant respectfully submits that the combination of Ramadass and Agarwal fail to render obvious the features "the host device comprising [...] one or more prefetch buffers storing the prefetch data" as recited in claims 1 and 14.
In the claimed disclosure, as the prefetch data is stored in the prefetch buffer, the cache controller can search the prefetch buffer for request data, which is data required by the host device. Accordingly, the speed at which the requested data is located can be improved.
On pages 3-4 of the Office Action, the Office asserted that the above-mentioned features of claim 1 are disclosed by paragraph [0021] of Agarwal, reciting "re-order buffers in reorder/retirement unit 135, ILTB 120, load/store buffers, and queues may be shared through partitioning."
Referring to paragraph [0021] and FIG. 1 of Agarwal, Agarwal teaches "re-order buffers in reorder retirement unit 135, ILTB 120, load store buffers, and queues may be shared through partitioning". However, regarding paragraph [0024] of Agarwal, Agarwal teaches "However, threads Ola and lib are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as reorder buffers to track instruction results" and "Reorder retirement unit 135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order". As such, Agarwal merely discloses that the re-order buffer and load/store buffer are used to track instruction results, support out-of-order execution, and support in-order retirement of instructions executed out of order. Agarwal does not disclose at all any content related to storing prefetch data to be prefetched from a memory expansion device to a host device, as required in claims 1 and 14.
The examiner respectfully disagrees and asserts that he combined teachings of Ramadass and Agrawal discloses the host device comprising one or more prefetch buffers storing the prefetch data. The applicant’s argument does not address the cited portions (¶0035; Hardware prefetch engines can help determine patterns and prefetch into a dedicated or a shared cache (mid-level cache or L2 cache or last level cache (LLC) prefetch).) that explicitly disclose prefetch engines that determine prefetch patterns and prefetch data into dedicated or shared cache. Agrawal and disclosed teaches the claim as seen in the rejection supra.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138