DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 18, 19, and 31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, a new reference of Lee et al. (US Pub. 2025/0225955 A1) is applied to a new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9-10, 12-15, 18-21, 28, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US Pub. 2023/0040656 A1) in view of Lee et al. (US Pub. 2025/0225955 A1).
Regarding claim 1; Wai teaches a method of controlling a display panel for a display driver circuit (a method of controlling a display control circuit system as shown in Fig.3), comprising:
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(Fig.6 of Wai reproduced)
starting counting time in a time period for receiving a first frame of display data (Fig.3, a timing control unit 301 sends a TE signal to a host 40 to instruct the host to transmit a frame data to a display driver 30. In Fig.6, para. [0059], the method comprises counting time from a first TE signal corresponding to a time when the GPU transmits a first frame data (i.e., circle around (1)) to the display driver 30. When the display driver 30 completely receives the first frame data, the display driver 30 sends a subsequent TE signal to instruct the host 40 to transmit a second frame data (i.e., circle around (2)) to the display driver 30), to generate a timing result (Fig.6, para. [0076-0077], the timing control unit 301 determines whether the transceiver unit 303 in the display driver 30 does not receive a Nth frame data within a preset time, the timing control unit 301 may send a second pulse B of the TE signal to instruct the GPU transmitting a new frame data to the display driver 30);
determining whether a timeout occurs according to the timing result (Figs.6 -8, para. [0076-0077], determining a time period T1 + S*T2, where S = 0 or 1); and
outputting a control signal to instruct a host processor to transmit a second frame of display data at a time when the timeout occurs (Figs.6-8, para.[0077-0095], the timing control unit 301 send a number of S (e.g., S=1) of second pulses B of the TE signal to instruct the GPU to send a third frame data to the display driver. For example, Fig.6, after a time period (T1+T2), the timing control unit 301 sends a pulse B of the TE signal to instruct the GPU to send a second frame data to the display driver 30. Generally, the timing control unit 301 would determine a time period (e.g., T1 + M*T3, para. [0008, 0013, 0018, and 0086]) to instruct the GPU to send a next frame data to the display driver).
Wai does not teach at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit.
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(Fig.2 of Lee reproduced)
Lee teaches at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit (Fig.2, para. [0037-0040 and 0043-0060], Lee discloses a method of transmitting image frames from a processor 110 to a display 115 via a first interface 111. In particular, the processor 110 may execute the image transmission based on a timing of the emission synchronization signal for the processor 110 synchronized with the emission synchronization signal for the display driver circuitry 120 within at least a portion 200 of the first time interval. For example, timings of the image transmission capable of being executed by the processor 110 within the at least a portion 200 of the first time interval may be indicated as the arrow 291. The portion 200 of the first time interval may include a time interval 201, a time interval 202, and a time interval 203. For example, a refresh rate corresponding to each of the time interval 201, the time interval 202, and the time interval 203 may be higher than a reference refresh rate. During the time interval 201, a first image is transmitted from the processor 110 to the display panel 140 for display without storing in a memory 130. Similarly, a second image and a third image are transmitted from the processor 110 to the display panel 140 for display without storing in the memory 130. In a time interval 204 having a refresh rate lower than or equal to the reference refresh rate, a fourth image transmitted from the processor 110 is stored in the memory 130. The display driver circuitry 120 may re-display the fourth image on the display panel 140 by scanning the fourth image stored in the memory 130, as indicated by the arrow 226).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the method of Wai of transmitting image frames from a host to a display device to include the teaching of Lee of determining whether a time interval is higher than a reference refresh rate; and directly transmitting an image frame from a processor to a display device if the time interval is higher than the refresh rate. The motivation would have been in order to provide a continuous, real-time streaming for dynamic content.
Regarding claim 2; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai teaches the display driver circuit is operated in a first operation mode, and the method further comprises: leaving the first operation mode to enter a second operation mode when the timeout occurs (Fig.8, the display driver is operated in a normal operation mode in the first frame and a self-refresh mode in a second frame and third frame. In particular, the first frame data is self-refreshed in the third frame, e.g., [0010, 0096]).
[AltContent: textbox (Self-refresh mode)][AltContent: arrow][AltContent: textbox (Normal refresh mode)][AltContent: arrow]
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(Fig.8 of Wai reproduced)
Regarding claim 9; Wai in view of Lee teaches the method of claim 2 as discussed above. Wai further teaches performing full refresh with a plurality of display data of a predetermined number of frames after entering the first operation mode from the second operation mode (referred to the analysis of claim 1, in Fig.8, Wai discloses that the display driver is operated in the first operation mode including a normal refresh mode (i.e., full refresh) and the second operation mode including a self-refresh mode. The operation mode is determined based on a time period for receiving a frame data by the data driver. For example, if the frame data is successfully received by the display driver within a preset time period T1, a TE signal is generated to instruct the GPU to send a next frame data to the display driver. However, if the frame data is not received by the display driver within the preset time period T1, the display driver may extend the display period (e.g., non-display period) until the frame data is received. Therefore, it would be understood that, after the third frame in Fig.8, the display driver may be operated in the normal refresh mode in a number of frames in which the display driver performs full refresh of frame data of the number of frames).
Regarding claim 10; Wai in view of Lee teaches the method of claim 2 as discussed above. Wai further teaches the display driver circuit is in the second operation mode (Fig.8, the self-refresh mode includes second frame and third frame), and the method further comprises: receiving a third frame of display data which is not in response to the control signal (Fig.8, para. [0094-0096], in the third frame, the display driver uses the first frame data ({circle around 1}) previously stored in a frame buffer, instead of receiving from the host); and leaving the second operation mode to enter the first operation mode when receiving the third frame of display data (It is understood that after the third frame, the display driver may be operated in the normal refresh mode if the display driver receives the frame data within the frame period).
Regarding claim 12; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai further teaches the step of starting counting time in the time period for receiving the first frame of display data comprises: starting counting time when receiving a synchronization signal for the first frame of display data (Fig.6-8, starting counting a time period (e.g., T1 + M*T3) when receiving a vertical synchronization V-sync).
Regarding claim 13; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai further teaches the step of starting counting time in the time period for receiving the first frame of display data comprises: starting counting time when the time period for receiving the first frame of display data starts (Fig.6-8, starting counting time when a TE signal starts. The TE signal is a starting time for receiving the frame data).
Regarding claim 14; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai further teaches the step of determining whether the timeout occurs according to the timing result comprises: determining that the timeout occurs when the timing result indicates that no vertical synchronization signal is received for a predetermined period of time (Fig.6, para. [0064, 0069-0070, 0074, and 0076], a vertical synchronization signal V-sync is generated after a pulse A of the TE signal. In a second frame, the vertical synchronization signal V-sync is not generated after pulse A of the TE signal because the display engine unit cannot send the second frame data to the display driver 30. A time period is determined after the pulse A of the TE signal until the second frame data is successfully transmitted from the GPU to the display driver 30. A vertical synchronization signal V-sync is generated after pulse B of the TE signal).
Regarding claim 15; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai further teaches performing full refresh with the second frame of display data (Fig.6, the second frame data (i.e., {circle around 2}) is fully transmitted to the display driver 30 for display in a third frame).
Regarding claim 18; Wai teaches a display driver circuit for controlling a display panel, to:
start counting time in a time period for receiving a first frame of display data, to generate a timing result (Figs. 6-8, Wai discloses a method of determining a time period for a display driver 30 to receive a frame data from a host in response to a TE signal. In particular, if the display driver successfully received the frame data within a preset time period T1, the TE signal is generated to instruct the host to send next frame data to the display driver. However, if the frame data is not received within the preset time period T1, the display driver extends the frame period to until the frame data is successfully received by the display driver);
determine whether a timeout occurs according to the timing result (Figs.6 -8, para. [0076-0077], determining a time period T1 + S*T2, where S = 0 or 1); and
output a control signal to instruct a host processor to transmit a second frame of display data at a time when the timeout occurs (Figs.6-8, para.[0077-0095], the timing control unit 301 send a number of S (e.g., S=1) of second pulses B of the TE signal to instruct the GPU to send a third frame data to the display driver. For example, Fig.6, after a time period (T1+T2), the timing control unit 301 sends a pulse B of the TE signal to instruct the GPU to send a second frame data to the display driver 30. Generally, the timing control unit 301 would determine a time period (e.g., T1 + M*T3, para. [0008, 0013, 0018, and 0086]) to instruct the GPU to send a next frame data to the display driver).
Wai does not teach at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit.
Lee teaches at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit (Fig.2, para. [0037-0040 and 0043-0060], Lee discloses a method of transmitting image frames from a processor 110 to a display 115 via a first interface 111. In particular, the processor 110 may execute the image transmission based on a timing of the emission synchronization signal for the processor 110 synchronized with the emission synchronization signal for the display driver circuitry 120 within at least a portion 200 of the first time interval. For example, timings of the image transmission capable of being executed by the processor 110 within the at least a portion 200 of the first time interval may be indicated as the arrow 291. The portion 200 of the first time interval may include a time interval 201, a time interval 202, and a time interval 203. For example, a refresh rate corresponding to each of the time interval 201, the time interval 202, and the time interval 203 may be higher than a reference refresh rate. During the time interval 201, a first image is transmitted from the processor 110 to the display panel 140 for display without storing in a memory 130. Similarly, a second image and a third image are transmitted from the processor 110 to the display panel 140 for display without storing in the memory 130. In a time interval 204 having a refresh rate lower than or equal to the reference refresh rate, a fourth image transmitted from the processor 110 is stored in the memory 130. The display driver circuitry 120 may re-display the fourth image on the display panel 140 by scanning the fourth image stored in the memory 130, as indicated by the arrow 226).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the method of Wai of transmitting image frames from a host to a display device to include the teaching of Lee of determining whether a time interval is higher than a reference refresh rate; and directly transmitting an image frame from a processor to a display device if the time interval is higher than the refresh rate. The motivation would have been in order to provide a continuous, real-time streaming for dynamic content.
Regarding claim 19; Wai teaches a method of controlling a display panel for a host processor (a GPU 401, Fig.3), comprising:
transmitting a first frame of display data to a display driver circuit for driving the display panel (Figs. 6-8, transmitting a first frame data ({circle around 1}) from a host (GPU) to a display driver 30);
receiving a control signal from the display driver circuit after transmitting the first frame of display data (Figs. 6-8, after a preset time period T1 from a first TE signal, when the display driver successfully receives the first frame data, the display driver 30 transmits a second TE signal to the host to instruct the host to send a next frame data); and
transmitting a second frame of display data in response to the control signal (Figs. 6-8, transmitting a second frame data ({circle around 2}) to the display driver).
Wai does not teach at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit.
Lee teaches at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit (Fig.2, para. [0037-0040 and 0043-0060], Lee discloses a method of transmitting image frames from a processor 110 to a display 115 via a first interface 111. In particular, the processor 110 may execute the image transmission based on a timing of the emission synchronization signal for the processor 110 synchronized with the emission synchronization signal for the display driver circuitry 120 within at least a portion 200 of the first time interval. For example, timings of the image transmission capable of being executed by the processor 110 within the at least a portion 200 of the first time interval may be indicated as the arrow 291. The portion 200 of the first time interval may include a time interval 201, a time interval 202, and a time interval 203. For example, a refresh rate corresponding to each of the time interval 201, the time interval 202, and the time interval 203 may be higher than a reference refresh rate. During the time interval 201, a first image is transmitted from the processor 110 to the display panel 140 for display without storing in a memory 130. Similarly, a second image and a third image are transmitted from the processor 110 to the display panel 140 for display without storing in the memory 130. In a time interval 204 having a refresh rate lower than or equal to the reference refresh rate, a fourth image transmitted from the processor 110 is stored in the memory 130. The display driver circuitry 120 may re-display the fourth image on the display panel 140 by scanning the fourth image stored in the memory 130, as indicated by the arrow 226).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the method of Wai of transmitting image frames from a host to a display device to include the teaching of Lee of determining whether a time interval is higher than a reference refresh rate; and directly transmitting an image frame from a processor to a display device if the time interval is higher than the refresh rate. The motivation would have been in order to provide a continuous, real-time streaming for dynamic content.
Regarding claim 20; Wai in view of Lee teaches the method of claim 19 as discussed above. Wai further teaches the control signal is generated according to a timing result of the display driver circuit (Figs. 6-8, para. [0097-0099], the TE signal is sent from the display driver 30 to the host, after the display driver 30 successfully receives a frame data, to instruct the host to send next frame data).
Regarding claim 21; Wai in view of Lee teaches the method of claim 19 as discussed above. The limitation of claim 21 is substantially similar to claim 2. Accordingly, claim 21 is rejected based on the same analysis as claim 2.
Regarding claim 28; Wai in view of Lee teaches the method of claim 21 as discussed above. The limitation of claim 28 is substantially similar to claim 10. Accordingly, claim 28 is rejected based on the same analysis as claim 10.
Regarding claim 31; Wai teaches a host processor (Fig.3, a host 40 comprises a GPU 401) for controlling a display panel, to:
transmit a first frame of display data to a display driver circuit for driving the display panel (Figs. 6-8, transmitting a first frame data ({circle around 1}) from a host (GPU) to a display driver 30);
receive a control signal from the display driver circuit after transmitting the first frame of display data (Figs. 6-8, after a preset time period T1 from a first TE signal, when the display driver successfully receives the first frame data, the display driver 30 transmits a second TE signal to the host to instruct the host to send a next frame data); and
transmit a second frame of display data in response to the control signal (Figs. 6-8, transmitting a second frame data ({circle around 2}) to the display driver).
Wai does not teach at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit.
Lee teaches at least one of the first frame of display data and the second frame of display data is forwarded to the display panel without being written into a frame buffer of the display driver circuit (Fig.2, para. [0037-0040 and 0043-0060], Lee discloses a method of transmitting image frames from a processor 110 to a display 115 via a first interface 111. In particular, the processor 110 may execute the image transmission based on a timing of the emission synchronization signal for the processor 110 synchronized with the emission synchronization signal for the display driver circuitry 120 within at least a portion 200 of the first time interval. For example, timings of the image transmission capable of being executed by the processor 110 within the at least a portion 200 of the first time interval may be indicated as the arrow 291. The portion 200 of the first time interval may include a time interval 201, a time interval 202, and a time interval 203. For example, a refresh rate corresponding to each of the time interval 201, the time interval 202, and the time interval 203 may be higher than a reference refresh rate. During the time interval 201, a first image is transmitted from the processor 110 to the display panel 140 for display without storing in a memory 130. Similarly, a second image and a third image are transmitted from the processor 110 to the display panel 140 for display without storing in the memory 130. In a time interval 204 having a refresh rate lower than or equal to the reference refresh rate, a fourth image transmitted from the processor 110 is stored in the memory 130. The display driver circuitry 120 may re-display the fourth image on the display panel 140 by scanning the fourth image stored in the memory 130, as indicated by the arrow 226).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the method of Wai of transmitting image frames from a host to a display device to include the teaching of Lee of determining whether a time interval is higher than a reference refresh rate; and directly transmitting an image frame from a processor to a display device if the time interval is higher than the refresh rate. The motivation would have been in order to provide a continuous, real-time streaming for dynamic content.
Claims 3-4 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US Pub. 2023/0040656 A1) in view of Lee et al. (US Pub. 2025/0225955 A1) as applied to claims 2 and 21 above; further in view of Yoon et al. (US Pub. 2025/0054440 A1).
Regarding claim 3; Wai in view of Lee teaches the method of claim 2 as discussed above. Wai does not teach the first operation mode comprises a multi-frequency display (MFD) operation, and the second operation mode does not comprise the MFD operation.
Yoon teaches the first operation mode comprises a multi-frequency display (MFD) operation, and the second operation mode does not comprise the MFD operation (Figs. 4 and 9, Yoon discloses a driving method in which a host AP transmits frame data to a driving controller 100 of a display panel DP. The display panel operates in a normal mode (NFM), a multi-frequency mode (MFM), and a refresh mode (RFM). In Fig.9, the display panel leaves the multi-frequency mode (MFM) in 4th frame to enter the refresh mode (RFM) in 5th frame).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Wai to include the teaching of Yoon of operating a display panel in different modes: multi-frequency mode, normal mode, and refresh mode. Accordingly, the first mode of Wai may be a multi-frequency mode. The motivation would have been in order to reduce power consumption without decreasing in the display quality (Yoon, para. [0166]).
Regarding claim 4; Wai in view of Lee and Yoon teaches the method of claim 3 as discussed above. Wai does not teach in the MFD operation, the display driver circuit performs partial refresh with the first frame of display data.
Yoon teaches in the MFD operation, the display driver circuit performs partial refresh with the first frame of display data (para. [0008], during the multi-frequency mode, the first display area may operate at a first driving frequency, and the second display area may operate at a second driving frequency lower from the first driving frequency. In other words, the display driver would partially refresh the frame data).
The motivation is the same as the rejection of claim 3.
Regarding claim 22; Wai in view of Lee teaches the method of claim 21 as discussed above. The limitation of claim 22 is substantially similar to claim 3. Accordingly, claim 22 is rejected based on the same analysis as claim 3.
Regarding claim 23; Wai in view of Lee and Yoon teaches the method of claim 22 as discussed above. The limitation of claim 23 is substantially similar to claim 4. Accordingly, claim 23 is rejected based on the same analysis as claim 4.
Claims 5-8, 11, 17, 24-27, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US Pub. 2023/0040656 A1) in view of Lee et al. (US Pub. 2025/0225955 A1) as applied to claims 2, 1, and 21 above; further in view of Yang et al. (US Pub. 2022/0351679 A1).
Regarding claim 5; Wai in view of Lee teaches the method of claim 2 as discussed above. Wai does not explicitly teach starting to receive a plurality of display data with sequentially down-converted frequencies in the second operation mode.
Yang teaches starting to receive a plurality of display data with sequentially down-converted frequencies in the second operation mode (Para. [0111], after the AP (i.e., host) detects the rising edge of TE, it detects whether the image data is ready. When the image data is ready, the image data is sent to the DDIC chip through MIPI; when the image data is not ready, a timeout duration (that is, how long it takes for the image data to be ready) is calculated and a timeout command is sent to the DDIC chip via MIPI such that the DDIC chip can adjust the relevant parameters according to the timeout command. Para. [0162], when the second image frame data is not received within the timer duration of the first timer, the refresh rate of the display screen is adjusted from 120 Hz to 90 Hz, and a second timer is set according to the second VFP extended duration. When the second image frame data is not received within the timer duration of the second timer, the refresh rate of the display screen is adjusted from 90 Hz to 60 Hz, and so on, until it is adjusted to the minimum refresh frequency (in case no second image data is ever received). In other words, frequencies of the frame data are sequentially down-converted until the image frame data is received by the DDIC chip).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Wai to include the teaching of Yang of down-converting frequencies of frame data until minimum frequency when the image data is received by the DDIC chip. The motivation would have been in order to reduce the influence of rate conversion on the screen display (Yang, para. [0048]).
Regarding claim 6; Wai in view of Lee and Yang teaches the method of claim 5 as discussed above. Wai further teaches the plurality of display data with the sequentially down-converted frequencies are triggered by outputting a plurality of control signals to the host processor (Fig.7, during a non-display period of second frame, the display driver 30 sending a plurality of TE signals to the host to extend the non-display period until the second frame data is successfully received by the display driver 30, [0084-0085]).
Regarding claim 7; Wai in view of Lee and Yang teaches the method of claim 5 as discussed above. Wai further teaches the plurality of display data keep unchanged when the display driver circuit is in the second operation mode (Fig.8, in the self-refresh mode, the first frame data is self-refreshed in the third frame).
Regarding claim 8; Wai in view of Lee and Yang teaches the method of claim 5 as discussed above. Wai further teaches the plurality of display data are transmitted with a start frequency, which is determined according to a timeout length (Figs. 6-8, frame data is transmitted with a TE signal which is determined based on a time period for successfully receiving the frame data).
Regarding claim 11; Wai in view of Lee teaches the method of claim 2 as discussed above. Wai further teaches the display driver circuit is in the first operation mode, and the method further comprises: outputting a plurality of control signals to instruct the host processor to transmit a plurality of entire frames of display data; receiving the plurality of entire frames of display data; and refreshing the display panel with the plurality of entire frames of display data (see the analysis of claim 2, Wai discloses that the first operation mode includes a normal refresh mode in which entire frame data is transmitted to the display driver for display).
Wai does not teach transmitting the frames of display data with sequentially down-converted frequencies; receiving the plurality of entire frames of display data; and refreshing the display panel with the plurality of entire frames of display data using the sequentially down-converted frequencies.
Yang teaches transmitting the frames of display data with sequentially down-converted frequencies; receiving the plurality of entire frames of display data; and refreshing the display panel with the plurality of entire frames of display data using the sequentially down-converted frequencies (Para. [0111], after the AP (i.e., host) detects the rising edge of TE, it detects whether the image data is ready. When the image data is ready, the image data is sent to the DDIC chip through MIPI; when the image data is not ready, a timeout duration (that is, how long it takes for the image data to be ready) is calculated and a timeout command is sent to the DDIC chip via MIPI such that the DDIC chip can adjust the relevant parameters according to the timeout command. Para. [0162], when the second image frame data is not received within the timer duration of the first timer, the refresh rate of the display screen is adjusted from 120 Hz to 90 Hz, and a second timer is set according to the second VFP extended duration. When the second image frame data is not received within the timer duration of the second timer, the refresh rate of the display screen is adjusted from 90 Hz to 60 Hz, and so on, until it is adjusted to the minimum refresh frequency (in case no second image data is ever received). In other words, frequencies of the frame data are sequentially down-converted until the image frame data is received by the DDIC chip).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Wai to include the teaching of Yang of down-converting frequencies of frame data until minimum frequency when the image data is received by the DDIC chip. The motivation would have been in order to reduce the influence of rate conversion on the screen display (Yang, para. [0048]).
Regarding claim 17; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai does not teach the display driver circuit comprises a timeout counter used for determining whether the timeout occurs.
Yang teaches the display driver circuit comprises a timeout counter used for determining whether the timeout occurs (para. [0073, 0154, and 0162], when a second image frame data is not received within VFP_120Hz, a DDIC chip sets a timeout timer according to a first VFP extended duration. When the second image frame data is not received within the timer duration of the first timer, the refresh rate of the display screen is adjusted from 120 Hz to 90 Hz, and a second timer is set according to the second VFP extended duration. When the second image frame data is not received within the timer duration of the second timer, the refresh rate of the display screen is adjusted from 90 Hz to 60 Hz, and so on, until it is adjusted to the minimum refresh frequency (in case no second image data is ever received).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Wai to include the timer of Yang for counting time in a VFP period until a frame data is received. The motivation would have been in order to reduce the influence of rate conversion on the screen display (Yang, para. [0048]).
Regarding claim 24; Wai in view of Lee teaches the method of claim 21 as discussed above. The limitation of claim 24 is substantially similar to claim 5. Accordingly, claim 24 is rejected based on the same analysis as claim 5.
Regarding claim 25; Wai in view of Lee and Yang teaches the method of claim 24 as discussed above. The limitation of claim 25 is substantially similar to claim 6. Accordingly, claim 25 is rejected based on the same analysis as claim 6.
Regarding claim 26; Wai in view of Lee and Yang teaches the method of claim 24 as discussed above. The limitation of claim 26 is substantially similar to claim 7. Accordingly, claim 26 is rejected based on the same analysis as claim 7.
Regarding claim 27; Wai in view of Lee and Yang teaches the method of claim 24 as discussed above. The limitation of claim 27 is substantially similar to claim 8. Accordingly, claim 27 is rejected based on the same analysis as claim 8.
Regarding claim 29; Wai in view of Lee teaches the method of claim 19 as discussed above. The limitation of claim 29 is substantially similar to claim 11. Accordingly, claim 29 is rejected based on the same analysis as claim 11.
Claims 16 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wai et al. (US Pub. 2023/0040656 A1) in view of Lee et al. (US Pub. 2025/0225955 A1) as applied to claims 1 and 21 above; further in view of Wu (US Pub. 2013/0300723 A1).
Regarding claim 16; Wai in view of Lee teaches the method of claim 1 as discussed above. Wai does not teach the display driver circuit is operated in a first operation mode, and the method further comprises: leaving the first operation mode to enter a second operation mode without being instructed by a command received from the host processor.
Wu teaches the display driver circuit is operated in a first operation mode, and the method further comprises: leaving the first operation mode to enter a second operation mode without being instructed by a command received from the host processor (Figs. 1-2, para. [0005, 0006, 0009, and 0012], Wu discloses a panel control device 100 for controlling a display panel 200. The panel control apparatus 100 comprises a scalar 110 and a timing controller 120. The scalar 110 is configured to keep the timing controller in a normal display mode or switch the timing controller to a self-refresh mode according to a state of a display image (e.g., static image or dynamic image). In other words, the panel control device does not receive a command to switch between refresh modes from a host processor).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Wai to include the teaching of Wu of providing a scalar configured to keep a timing controller in a normal display mode or self-refresh mode based on determining whether display image is static or dynamic. The motivation would have been in order to reduce image quality differences of a display image when an operation mode switches and to an operation method thereof (Wu, para. [0002 and 0007]).
Regarding claim 30; Wai in view of Lee teaches the method of claim 21 as discussed above. The limitation of claim 30 is substantially similar to claim 16. Accordingly, claim 30 is rejected based on the same analysis as claim 16.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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