DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,132,470. Although the claims at issue are not identical, they are not patentably distinct from each other because claim of the instant application is directed to essentially similar limitation as in claim 1 of US Patent No. 12,132,470. Claim 1 of the instant application is broader than claim 1 of U.S. Patent No. 12,132,470 by omitting other features recited in claim 1 of U.S. Patent No. 12,132,470 such as “a GaN FET power switch; and a driver for the GaN FET power switch, the driver including: a reference device for generating a reference voltage, a GaN-based under-voltage detector having a first input terminal receiving a supply voltage, a second input terminal for receiving a voltage at ground potential, a third input terminal receiving the reference voltage, and an output terminal, wherein the reference voltage is referred to the supply voltage, and wherein the GaN-based under-voltage detector outputs an under voltage lock-out signal when the supply voltage is below a low-to-high threshold value, and does not output the under voltage lock-out signal when the supply voltage is above the low-to-high threshold value and for a predetermined amount of time after the supply voltage first rises above the low-to-high threshold value ”
Instant application 18/928390
US Patent US 12,132,470
1. An under voltage lock-out circuit for producing an undervoltage lock-out signal upon detection of an under-voltage condition of a supply voltage. comprising: a supply voltage input; an under voltage lock-out signal output; and
a pulse stretcher comprising an input terminal coupled to the under voltage lock-out signal output, the pulse stretcher operating to produce a stretched under voltage lock-out signal based on receipt of an under-voltage condition indication on the undervoltage lock-out signal output, wherein the pulse stretcher includes: a first stretcher transistor having a drain, a source coupled to ground potential, and a gate coupled to the input terminal of the pulse stretcher, a first stretcher resistor coupled between the supply voltage input and the drain of the first stretcher transistor, a second stretcher resistor having one end coupled to the drain of the first stretcher transistor, a first capacitor coupled between another end of the second stretcher resistor and ground potential, a first diode having an anode coupled to the other end of the second stretcher resistor, a third stretcher resistor having one end coupled to a cathode of the first diode, a second capacitor coupled between another end of the third stretcher resistor and ground potential, a second diode having an anode coupled to another end of the third stretcher resistor, a third diode having an anode coupled to ground potential. a second stretcher transistor having a drain coupled to the other end of the third stretcher resistor, a source coupled to ground potential, and a gate coupled to the input terminal of the pulse stretcher, a third stretcher transistor having a drain, a gate coupled to the other end of the third stretcher resistor, and a source coupled to ground potential, and a fourth resistor coupled between the supply voltage input and the drain of the third stretcher transistor, wherein the stretched under voltage lock-out signal is produced at the drain of the third stretcher transistor.
1. An electronic circuit comprising: a GaN FET power switch; and a driver for the GaN FET power switch, the driver including: a reference device for generating a reference voltage, a GaN-based under-voltage detector having a first input terminal receiving a supply voltage, a second input terminal for receiving a voltage at ground potential, a third input terminal receiving the reference voltage, and an output terminal, wherein the reference voltage is referred to the supply voltage, and wherein the GaN-based under-voltage detector outputs an under voltage lock-out signal when the supply voltage is below a low-to-high threshold value, and does not output the under voltage lock-out signal when the supply voltage is above the low-to-high threshold value, and a pulse stretcher having an input terminal coupled to the output terminal of the GaN-based under-voltage detector, and an output terminal for outputting a stretched under voltage lock-out signal for a predetermined amount of time after the supply voltage first rises above the low-to-high threshold value, the pulse stretcher comprising: a first transistor having a drain, a source coupled to ground potential, and a gate coupled to the input terminal of the pulse stretcher, a first resistor coupled between the supply voltage and the drain of the first transistor,
a second resistor having one end coupled to the drain of the first transistor, a first capacitor coupled between another end of the second resistor and ground potential, a first diode having an anode coupled to the other end of the second resistor, a third resistor having one end coupled to a cathode of the first diode, a second capacitor coupled between another end of the third resistor and ground potential, a second diode having an anode coupled to another end of the third resistor, a third diode having an anode coupled to a cathode of the second diode and a cathode coupled to ground potential, a second transistor having a drain coupled to the other end of the third resistor, a source coupled to ground potential, and a gate coupled to the input terminal of the pulse stretcher, a third transistor having a drain, a gate coupled to the other end of the third resistor, and a source coupled to ground potential, and a fourth resistor coupled between the supply voltage and the drain of the third transistor, wherein the stretched under voltage lock-out signal is produced at the drain of the third transistor.
Allowable Subject Matter
Claims 8-10, 12-13 and 15-24 are allowed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
Prosecution Insights