DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 8-9, 11-12, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Brohlin (US 6842321) in view of Kobayashi et al. (US 2019/0109589 and Kobayashi hereinafter).
Regarding claim 1, Brohlin discloses an under voltage lock-out circuit [fig. 3], comprising: a supply voltage input [input Vss]; an under voltage lock-out signal output [UVLO]; a reference voltage circuit interface [interface (node) of voltage divider R5 and R2]; a first transistor [Q3] having: a first source [source Q3] and a first gate [gate Q3] both coupled to the supply voltage input; and a drain first [drain Q3] coupled to a first port [node between R5 and Q3] of the reference voltage circuit interface [voltage divider R5 and R2]; a second transistor [Q6] having: a second gate [gate Q6] coupled to the first drain via a second port of the reference voltage circuit interface [node between R5 and R2]; a second drain [drain Q6] coupled to the under voltage lock-out signal output [through M1] and coupled, via a first resistor [R2], to the supply voltage input; and a second source [source Q6] coupled, via a second resistor [not labeled resistor between Q6 and PBKG ], to a ground potential [PBKG]; a third transistor [M1] having: a third gate [gate M1] coupled to the under voltage lock-out signal output; a third drain [drain M1] coupled through a third resistor [R5] to the first source; and a third source [source M1] coupled to the second drain. Brohlin does not explicitly disclose the GaN technology.
However, Kobayashi discloses an undervoltage lock-out transistor with GaN technology [par. 101]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Brohlin by incorporating the GaN technology as taught in Kobayashi in order to provide well known faster switching and improved efficiency compared to MOSFETs.
Regarding claim 2, Brohlin in view of Kobayashi discloses [cl. 2, ln. 21-39, ref. Brohlin / par. 105, ref. Kobayashi] wherein a value of the first resistor and a value of the third resistor are chosen to provide a hysteresis value defining a difference between a low-to-high threshold value and a high-to-low threshold value of voltages present on the supply voltage input that cause a change of state of the under-voltage lock-out signal output.
Regarding claim 4, Brohlin in view of Kobayashi discloses [fig. 3] further comprising a voltage reference [voltage divider] that comprises a resister divider [R5/R2] coupled to the first port and the second port, wherein the first port is coupled to an input of the resister divider [node between Q3 and R5] and the second port is coupled to a node between resisters of the resister divider [node between R5 and R2].
Regarding claim 5, Brohlin in view of Kobayashi discloses further comprising a voltage reference [bandgap voltage, cl. 2, lines 21-49] coupled to the reference voltage circuit interface, the voltage reference comprising an external bandgap voltage reference [fig. 7, ref. Kobayashi], wherein the first port is coupled to a first connection of the external bandgap voltage reference and the second port is coupled to a second connection of the external bandgap voltage reference [fig. 3].
Regarding claim 8, Brohlin discloses an electronic circuit [see fig. 3] comprising: an under voltage lock-out signal output [UVLO]; a first transistor [Q3] having: a first source [source Q3] and a first gate [gate Q3] both coupled to a supply voltage input [Vss]; and a first drain [drain Q3] coupled to a first port [node between R5 and Q3] of a reference device [voltage divider R5 and R2]; a second transistor [Q6] having: a second gate [gate Q6] coupled to the first drain via a second port of the reference device [via node between R5 and R2]; a second drain [drain Q6] coupled to the under voltage lock-out signal output and coupled, via a first resistor [R2], to the supply voltage input; and a second source [source Q6] coupled, via a second resistor [not labeled resistor between Q6 and PBKG], to a ground potential [PBKG]; a third transistor [M1] having: a third gate [gate M1] coupled to the under voltage lock-out signal output; a third drain [drain M1] coupled through a third resistor [R5] to the first source; and a third source [source M1] coupled to the second drain. Brohlin does not explicitly disclose a GaN FET power switch; and a driver for the GaN FET power switch, the driver comprising: a reference device for generating a reference voltage, a GaN-based under-voltage detector, an under-voltage lock-out signal output coupled one of directly or indirectly to the GaN FET power switch and the GaN technology.
However, Kobayashi discloses [see figs. 5 and 7-10] a GaN FET power switch [MNT, fig. 7]; and a driver [Vref and LPF, fig. 7] for the GaN FET power switch, the driver comprising: a reference device [external] for generating a reference voltage [Vref], a GaN-based under-voltage detector [par. 101], an under-voltage lock-out signal output [UVLO] coupled one of directly or indirectly to the GaN FET power switch and teaches he GaN technology. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Brohlin by incorporating the invention as taught in Kobayashi in order to drive GaN transistor to ensure efficient and reliable operation.
Regarding claim 9, Brohlin in view of Kobayashi discloses [cl. 2, ln. 21-39, ref. Brohlin / par. 105, ref. Kobayashi] wherein a value of the first resistor and a value of the second resistor are chosen to provide a hysteresis value defining a difference between a positive-going threshold and a negative going threshold of voltages present on the supply voltage input that cause a change of state of the under-voltage lock-out signal output.
Regarding claim 11, Brohlin in view of Kobayashi discloses [fig. 3] wherein the reference device [voltage divider] comprises a resister divider [R5/R2], wherein the first port comprises an input to the resister divider [node between Q3 and R5] and the second port comprises a connection to a node between two resisters of the resister divider [node between R5 and R2].
Regarding claim 12, Brohlin in view of Kobayashi discloses [fig. 3] wherein the reference device comprises an external bandgap voltage reference [bandgap voltage, cl. 2, lines 21-49/see also fig. 7, ref. Kobayashi], and the first port comprises a first connection of the external bandgap voltage reference and the second port comprises an electrical coupling between a second connection of the bandgap voltage reference and a third resistor connecting the second connection to the ground potential [fig. 3].
Regarding claim 15, Brohlin discloses under-voltage detector [see fig. 3] comprising: a first transistor [Q3] having: a first source [source Q3] and a first gate [gate Q3] both coupled to the input terminal; and a first drain [drain Q3] coupled to a first port [node between R5 and Q3]of reference voltage circuit interface [voltage divider R5 and R2]; a second transistor [Q6] having: a second gate [gate Q6]coupled to the first drain via a second port of the reference voltage circuit interface [via node between R5 and R2]; a second drain [drain Q6] coupled to the under voltage lock-out signal output and coupled, via a first resistor [R2], to the input terminal; and a second source [source Q6] coupled, via a second resistor [not labeled resistor between Q6 and PBKG], to a ground potential [PBKG]; a third GaN transistor having: a third gate [M1] coupled to an under voltage lock-out signal output [UVLO]; a third drain [drain M1] coupled through a third resistor [R5] to the first source; and a third source [source M1] coupled to the second drain. Brohlin does not explicitly disclose a substrate; a GaN FET power switch disposed on the substrate; and a GaN-based driver disposed on the substrate and coupled to the GaN FET power switch, the GaN-based driver having an input terminal for receiving a supply voltage, the GaN-based driver comprising: a reference voltage circuit interface; an under voltage lock-out signal output that is coupled one of directly or indirectly to the GaN FET power switch; a GaN transistor technology; and wherein the GaN-based under-voltage detector outputs the under-voltage lock-out signal when the supply voltage is below a low-to-high threshold value, and does not output the under-voltage lock-out signal when the supply voltage is above the low-to-high threshold value.
However, in the same field of endeavor Kobayashi discloses [see figs. 5 and 7-10], comprising: a substrate [par. 101]; a GaN FET power switch [MNT. Fig. 7] disposed on the substrate; and a GaN-based driver [Vref and LPF, fig. 7] disposed on the substrate and coupled to the GaN FET power switch, the GaN-based driver having an input terminal [first input terminal to Vdd] for receiving a supply voltage [Vdd], the GaN-based driver comprising: a reference voltage circuit interface; an under voltage lock-out signal output [DOUT] that is coupled one of directly or indirectly to the GaN FET power switch; wherein the GaN-based under-voltage detector outputs the under-voltage lock-out signal when the supply voltage is below a low-to-high threshold value, and does not output the under-voltage lock-out signal when the supply voltage is above the low-to-high threshold value [see par. 0007, 0093-0095 and 117-120]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Brohlin by incorporating the invention as taught in Kobayashi in order to drive GaN transistor to ensure efficient and reliable operation.
Regarding claim 20, Brohlin in view of Kobayashi discloses [see fig. 3] wherein the predetermined amount of time increases as the ramp rate of the supply voltage decreases.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Brohlin in view of Kobayashi et al.
Regarding claim 16, Brohlin in view of Kobayashi discloses all aspects of the instant invention. Brohlin in view of Kobayashi discloses further discloses the third GaN transistor are each a respective N-channel enhancement-mode GaN high-electron-mobility transistor. Brohlin in view of Kobayashi does not explicitly disclose the first GaN transistor, the second GaN transistor are each a respective N-channel enhancement-mode GaN high-electron-mobility transistor. These transistors are just different types of transistors and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Regarding claim 17, Brohlin in view of Kobayashi discloses all aspects of the instant invention, except for a minimum low-to-high threshold value is greater than 2 times threshold voltage of fabrication process of the totally-GaN-based driver. However, it is noted that the specification fails to provide teachings about the criticality of having a minimum low-to-high threshold value is greater than 2 times threshold voltage of fabrication process, as claimed in the instant application. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 18, Brohlin in view of Kobayashi discloses wherein the minimum low-to-high threshold tracks a threshold voltage of a fabrication process of the GaN-based driver.
3. Claims 3, 6, 10, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Brohlin in view of Kobayashi et al. further in view of Suh et al. (US 2018/0269863 and Suh hereinafter).
Regarding claims 6, 13 and 19, Brohlin in view of Kobayashi discloses all the features with respect to claims 1, 8 and 15 as outlined above. Brohlin in view of Kobayashi does not explicitly disclose a pulse stretcher comprising an input terminal coupled to the under-voltage lock-out signal output, the pulse stretcher operating to produce a stretched under voltage lock-out output for a predetermined amount of time based on receipt of an indication on the under-voltage lock-out signal output, wherein the predetermined amount of time is a function of ramp rate of the supply voltage.
However, Suh discloses a pulse stretcher [80, fig. 6] comprising an input terminal [input to FO] coupled to the under-voltage lock-out signal output [output 90], the pulse stretcher operating to produce a stretched under voltage lock-out output [extended signal FO, fig. 7] for a predetermined amount of time based on receipt of an indication [Fault indicator FO, fig. 7] on the under-voltage lock-out signal output, wherein the predetermined amount of time [duration 250µs] is a function of ramp rate of the supply voltage [fig. 7]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Brohlin in view of Kobayashi by incorporating the pulse stretcher as taught in Suh in order to provides a guard band to ensure the normal operation is not resumed immediately after a fault is removed [para. 0062].
Regarding claims 3 and 10, Brohlin in view of Kobayashi discloses all the features with respect to claims 1 and 8 as outlined above. Brohlin in view of Kobayashi does not explicitly disclose wherein the first GaN transistor, the second GaN transistor, and the third GaN transistor are formed on a single substrate.
However, Suh discloses [see fig. 3] under-voltage lock-out [inside 65, see fig. 5] formed on a single substrate. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Brohlin in view of Kobayashi by incorporating single substrate as taught in Suh in order to have a one-piece, compact construction.
Allowable Subject Matter
Claims 7 and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842