DETAILED ACTION
This action is in response to the Application filed on 10/28/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/28/2024, 12/10/2024 and 07/08/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 3 and 5 – 11 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 2, 4 and 7 of U.S. Patent No. 12,166,420. Although the claims at issue are not identical, they are not patentably distinct from each other because all the features of the Instant Application are claimed in U.S. Patent No. 12,166,420, as indicated in the comparison table below.
Instant Application 18928401
US Patent No. 12,166,420
1. An output feedback control circuit, comprising:
a first amplifier configured to generate an error signal corresponding to a difference between an output voltage, which is fed to a load, or a voltage based on the output voltage, and a reference voltage;
a second amplifier configured to generate an output signal based on a difference between the output voltage or the voltage based on the output voltage and the error signal or the reference voltage;
a calculator configured to add a remote sense signal which is derived from a grounded terminal of the load and to output the reference voltage; and
a remote sense signal application terminal configured such that a capacitor is to be connected between the remote sense signal application terminal and an output terminal of the first amplifier.
5. The output feedback control circuit according to claim 1, wherein the second amplifier configured to be faster than the first amplifier.
7. An output feedback control circuit, comprising:
a first amplifier configured to generate an error signal corresponding to a difference between an output voltage, which is fed to a load, or a voltage based on the output voltage, and a reference voltage;
a second amplifier configured to generate an output signal based on a difference between the output voltage or the voltage based on the output voltage and the error signal;
a calculator configured to superimpose a remote sense signal, which is derived from a grounded terminal of the load, on a predetermined voltage that is corresponding to a target value of the output voltage and to output the reference voltage; and
a remote sense signal application terminal configured such that a capacitor is to be connected between the remote sense signal application terminal and an output terminal of the first amplifier.
10. The output feedback control circuit according to claim 7, wherein the second amplifier is configured to be faster than the first amplifier.
1. An output feedback control circuit, comprising:
a first amplifier configured to generate a first error signal commensurate with a difference between an output voltage, which is fed to a load, or a feedback voltage commensurate therewith, and a predetermined reference voltage;
a second amplifier configured to be faster than the first amplifier and to generate a second error signal commensurate with a difference between the output voltage or the feedback voltage and the first error signal or the predetermined reference voltage;
a calculator configured to superimpose a remote sense signal, which is derived from a grounded terminal of the load, on the reference voltage, which is fed to the first amplifier; and a capacitor connected between an application terminal for the first error signal and an application terminal for the remote sense signal.
2. The output feedback control circuit according to claim 1, wherein to an output terminal of the second amplifier, no capacitor other than a parasitic element is connected.
8. The output feedback control circuit according to claim 7, wherein to an output terminal of the second amplifier, no capacitor other than a parasitic element is connected.
2. The output feedback control circuit according to claim 1, wherein to an output terminal of the second amplifier, no capacitor other than a parasitic element is connected.
The output feedback control circuit according to claim 1, wherein the first amplifier is configured to have a first transconductance.
9. The output feedback control circuit according to claim 7, wherein the first amplifier is configured to have a first transconductance.
4. The output feedback control circuit according to claim 1, wherein the first amplifier is configured to have a first transconductance, and the second amplifier is configured to have a second transconductance different from the first transconductance.
A switching power supply, comprising: the output feedback control circuit according to claim 1; and a switching output circuit configured to generate the output voltage from an input voltage to feed the output voltage to the load, wherein the output feedback control circuit is configured to perform output feedback control of the switching output circuit.
11. A switching power supply, comprising: the output feedback control circuit according to claim 7; and a switching output circuit configured to generate the output voltage from an input voltage to feed the output voltage to the load, wherein the output feedback control circuit is configured to perform output feedback control of the switching output circuit.
7. A switching power supply, comprising: the output feedback control circuit according to claim 6; and a switching output circuit configured to generate the output voltage from an input voltage to feed the output voltage to the load, wherein; the output feedback control circuit is configured to receive the output voltage or the feedback voltage commensurate therewith and the remote sense signal, which is derived from the grounded terminal of the load, to perform output feedback control of the switching output circuit.
Examiner's Note
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 4 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 4 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the calculator configured to superimpose the remote sense signal on a predetermined voltage that is corresponding to a target value of the output voltage.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent No. 10,727,732 discloses an active line filter.
US Pub. No. 2016/0351146 discloses an adder unit that adds an offset voltage to a reference voltage so as to generate the threshold value voltage. In other words, the threshold value voltage is set in a variable manner on the basis of the reference voltage.
US Pub. No. 2013/0002212 discloses a feedback circuit with a reference adjust circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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