DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-4 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 3 of U.S. Patent No. 12,218,233. Although the claims at issue are not identical, they are not patentably distinct from each other.
[Re claim 1] Oh discloses the high electron mobility transistor comprising: a channel layer including a first semiconductor material; a channel supplying layer including a second semiconductor material and causing generation of a two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supplying layer; a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG; a gate electrode provided on a portion of the depletion forming layer; and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer, and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode, wherein the gate electrode comprises an upper portion in contact with an upper surface of the current limiting layer and a lower portion in contact with a side surface of the current limiting layer, wherein the depletion forming layer is of an integral type and extends in a direction parallel to the gate electrode, wherein the current limiting layer is respectively provided on both sides of a lower side of the gate electrode, and wherein the current limiting layer includes portions spaced apart from each other in a direction parallel to the gate electrode (see claim 1 and 3).
[Re claim 2] Oh discloses the high electron mobility transistor comprising: a channel layer including a first semiconductor material; a channel supplying layer including a second semiconductor material and causing generation of a two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supplying layer; a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG; a gate electrode provided on a portion of the depletion forming layer; and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer, and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode, wherein the gate electrode comprises an upper portion in contact with an upper surface of the current limiting layer and a lower portion in contact with a side surface of the current limiting layer, and wherein the depletion forming layer has portions spaced apart from each other in a direction parallel to the gate electrode (see claim 1).
[Re claim 3] Oh discloses the high electron mobility transistor, wherein the current limiting layer is respectively provided on both sides of a lower side of the gate electrode (see claim 3).
[Re claim 4] Oh discloses the high electron mobility transistor, wherein the current limiting layer is of an integral type and extends in a direction parallel to the gate electrode (see claim 1).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by OTAKE et al. (US Patent Appl. Pub. No. 2020/0176595 A1).
[Re claim 1] OTAKE discloses the high electron mobility transistor comprising: a channel layer (4) including a first semiconductor material (GaN); a channel supplying layer (5) including a second semiconductor material (A1x1Ga1-x1N) and causing generation of a two-dimensional electron gas (2DEG) (11) in the channel layer; a source electrode (9) and a drain electrode (10) provided on both sides of the channel supplying layer; a depletion forming layer (21) provided on the channel supplying layer to form a depletion region (area under the layer 21) in the 2DEG; a gate electrode (23) provided on a portion of the depletion forming layer (21); and a current limiting layer (22) provided to contact the gate electrode on another portion of the depletion forming layer, and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode (the limiting layer 22 provided to contact the gate electrode 23 and reduce current leakage from the gate electrode and this will limit the current flow when the voltage is applied), wherein the gate electrode (23) comprises an upper portion in contact with an upper surface of the current limiting layer (22) and a lower portion in contact with a side surface of the current limiting layer (22), wherein the depletion forming layer (21) is of an integral type and extends in a direction parallel to the gate electrode (23), wherein the current limiting layer (22) is respectively provided on both sides of a lower side of the gate electrode (23), and wherein the current limiting layer (22) includes portions spaced apart from each other in a direction parallel to the gate electrode (23) (see figure 1 and paragraph [0048]-[0059]).
[Re claim 2] OTAKE discloses the high electron mobility transistor comprising: a channel layer (4) including a first semiconductor material (GaN); a channel supplying layer (5) including a second semiconductor material (A1x1Ga1-x1N) and causing generation of a two-dimensional electron gas (2DEG) (11) in the channel layer; a source electrode (9) and a drain electrode (10) provided on both sides of the channel supplying layer; a depletion forming layer (21) provided on the channel supplying layer to form a depletion region (area under the layer 21) in the 2DEG; a gate electrode (23) provided on a portion of the depletion forming layer; and a current limiting layer (22) provided to contact the gate electrode (23) on another portion of the depletion forming layer (21), and configured to limit a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode (the limiting layer 22 provided to contact the gate electrode 23 and reduce current leakage from the gate electrode and this will limit the current flow when the voltage is applied), wherein the gate electrode (23) comprises an upper portion in contact with an upper surface of the current limiting layer (22) and a lower portion in contact with a side surface of the current limiting layer (22), and wherein the depletion forming layer (21) has portions (areas contacting with current limiting layer 22) spaced apart from each other in a direction parallel to the gate electrode (see figure 1 and paragraph [0048]-[0059]).
[Re claim 3] OTAKE discloses the high electron mobility transistor, wherein the current limiting layer (22) is respectively provided on both sides of a lower side of the gate electrode (23) (see figure 1 and paragraph [0055]-[0058]).
[Re claim 4] OTAKE discloses the high electron mobility transistor, wherein the current limiting layer (22) is of an integral type and extends in a direction parallel to the gate electrode (23) (see figure 1 and paragraph [0055]-[0058]).
[Re claim 5] OTAKE discloses the high electron mobility transistor wherein the current limiting layer (22) includes portions spaced apart from each other in a direction parallel to the gate electrode (23) (see figure 1).
[Re claim 6] OTAKE discloses the high electron mobility transistor wherein the current limiting layer (22) surrounds a lower portion of the gate electrode (23) (see figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817
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