DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered.
Claim status
Claims 1-11 and 13-18 are pending; claims 1 is independent. Claim 12 has been cancelled.
Response to Arguments
Applicant's arguments filed 04/22/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments, pages 1-2, that (1) Tamura's capacitances 26 and 27 are not a holding transistor as claimed, and (2) there has been no showing that one having ordinary skill in the art would wish to replace such capacitances with the claimed holding transistor.
However, the examiner respectfully disagrees, Tamura discloses wherein the holding transistor is configured to provide (1) a first capacitance between the gate and the source of the driving transistor and (Tamura, fig. 2 and Para 0076, a capacitance 26 is connected between the gate electrode and the source electrode of the driving transistor 22) (2) a second capacitance between the source of the driving transistor and a power supply line (Tamura, fig. 2 and Para 0076, a capacitance 27 is connected between the source electrode of the driving transistor 22, and a node of a fixed electrical potential, Yang discloses in fig. 2 and Para 0072, One or both of the variable capacitors 106, 108 may be TFT-based metal-insulator-semiconductor (MIS) capacitors constructed by connecting a source and a drain of TFT. TFT with its source and drain being connected together is an example of a variable capacitor, wherein the gate terminal of the variable capacitor 106, 108 can be defined as the gate of the TFT, the source terminal of the variable capacitor 106, 108 can be defined as the source of the TFT, which is connected to the drain of the TFT, see also fig. 26 and par 0133, a variable capacitor (T.sub.3) functions as a transistor. The motivation being to improve the stability of the drain-to-source current in the driving phase by using the variable capacitor to generate the compensation voltage so as to compensate for threshold voltage shift of drive transistor, as known technique to yield a predictable result.
In response to applicant’s arguments, pages 1-2, that Yang provides neither a description nor a suggestion of the threshold voltage of the holding transistor (configured as claimed) being lower than the threshold voltage of the driving transistor,
However, the examiner respectfully disagrees Yang taught in in Paras 0073 and 0077, wherein when the gate-to-source voltage of the n-type TFT is higher enough than its threshold voltage, the total capacitance of the n-type TFT is equal to the channel capacitance plus the sum of the source and drain overlap capacitances. When the gate-to-source voltage of the n-type TFT is lower enough than its threshold voltage, the total capacitance of the n-type TFT is equal to the sum of its source and drain overlap capacitances. When the gate-to-source voltage of the n-type TFT is higher than its threshold voltage, the amount of the charge stored in the n-type TFT decreases with the increase of its VT. Since the gate of the first variable capacitor 106, “as a part to form the threshold transistor” and the gate of drive transistor 102 are stressed by the same voltage (i.e., the voltage on node A 116, fig. 2), the DELTAT of the first variable capacitor 106 tracks the .DELTAVT of the drive transistor 102. The DELTAT of the first variable capacitor 106 results in the change of the charge drawn by the first variable capacitor 106 from the gate of the drive transistor 102 in the driving phase, and therefore results in the change of the gate voltage of the drive transistor 102 with the DELTAVT of the drive transistor 102. The stability of the drain-to-source current 111 in the driving phase is improved by using the first variable capacitor 106 to generate the compensation voltage so as to compensate for threshold voltage shift of drive transistor 102, see fig. 2 and para 0077, Yang.
More explanation, generally speaking, the threshold voltage of a transistor is the minimum gate-to-source voltage required to form a conductive channel between the source and drain, turning the transistor on. It is a critical parameter for switching, Yang disclose The variable capacitor 56, 58 is a component with at least two terminals, including a gate and a source (as defined herein) of the variable capacitor 56, 58. The variable capacitor 56, 58 has a threshold voltage (VT) and a gate-to-source voltage (V.sub.gs). The V.sub.gs of the variable capacitor 56, 58 is a voltage difference between the gate and source of the variable capacitor 56, 58. Which terminal is the gate of the variable capacitor 56, 58 and which terminal is the source of the variable capacitor 56, 58 is defined such that the definition of the V.sub.gs of the variable capacitor 56, 58 is in accordance to the following descriptions of the dependence of the capacitance of the variable capacitor 56, 58 on the V.sub.gs of the variable capacitor 56, 58. The capacitance of the variable capacitor 56, 58 may be dependent on the V.sub.gs of the variable capacitor 56, 58 (Para 0068). So V.sub.gs depend on the capacitance of the variable capacitor , so the minimum gate-to-source voltage (threshold voltage) is not constant for the variable capacitor (hold transistor) and could be lower than the drive transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-11 and 13-14, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura (US 2019/0123124), and further in view of Yang (US 2015/0084538).
Regarding claim 1, Tamura teaches a light emitting device (figs 1 and 2) comprising:
a light emitting element (fig. 2 and an organic EL element 21);
a driving transistor (fig. 2 and a driving transistor 22) and a switching transistor (fig. 2 and a light emitting control transistor 24 ) each arranged on a path where a current for causing the light emitting element to emit light flows (fig. 2 and Para 0075, wherein the light emitting control transistor 24 is connected between a power line of the power electrical voltage Vcc and a source electrode of the driving transistor 22, and performs the control of the light emitting/non-light emitting of the organic EL element 21);
a writing transistor arranged on a path connecting a signal line to which a pixel signal is supplied and a gate of the driving transistor (fig. 2 and Para 0075, wherein the writing transistor 23 writes the signal electrical voltage Vsig which is supplied from the signal output unit 60 through the signal line 34, in a gate electrode of the driving transistor 22, by sampling the signal electrical voltage Vsig); and
a holding transistor configured to hold a gate-source voltage of the driving transistor (fig. 2, the combination of the retentive capacitance 26 and the auxiliary capacitance 27 and Para 0076),
wherein a gate of the holding transistor is connected to the gate of the driving transistor, wherein each of a source and a drain of the holding transistor is connected to a source of the driving transistor (fig. 2, the combination of the retentive capacitance 26 and the auxiliary capacitance 27 and Para 0076 function as a holding transistor,
wherein the holding transistor and the switching transistor are formed in a same impurity region (fig. 4 and Paras 0110-0115, wherein the driving transistor 22, the writing transistor 23, the light emitting control transistor 24, and the switching transistor 25, including a p-channel type transistor, are disposed on an n type semiconductor substrate 71 including silicon “Para 0110”. The wiring 74 is used as one electrode of the retentive capacitance 26, and the wiring 75 is used as the other electrode of the retentive capacitance 26, are disposed on an n type semiconductor substrate 71, “Para 0112”. The auxiliary capacitance 27 is built in the semiconductor substrate 71 “Para 0121”), and
Tamura does not expressly disclose a holding transistor functions as two capacitances; wherein a conductivity type of the holding transistor is the same as a conductivity type of the driving transistor, and Wherein the holding transistor is configured to provide (1) a first capacitance between the gate and the source of the driving transistor and (2) a second capacitance between the source of the driving transistor and a power supply line.
However, Tamura discloses wherein the holding transistor is configured to provide (1) a first capacitance between the gate and the source of the driving transistor and (Tamura, fig. 2 and Para 0076, a capacitance 26 is connected between the gate electrode and the source electrode of the driving transistor 22) (2) a second capacitance between the source of the driving transistor and a power supply line (Tamura, fig. 2 and Para 0076, a capacitance 27 is connected between the source electrode of the driving transistor 22, and a node of a fixed electrical potential, Yang discloses in fig. 2 and Para 0072, One or both of the variable capacitors 106, 108 may be TFT-based metal-insulator-semiconductor (MIS) capacitors constructed by connecting a source and a drain of TFT. TFT with its source and drain being connected together is an example of a variable capacitor, wherein the gate terminal of the variable capacitor 106, 108 can be defined as the gate of the TFT, the source terminal of the variable capacitor 106, 108 can be defined as the source of the TFT, which is connected to the drain of the TFT, see also fig. 26 and par 0133, a variable capacitor (T.sub.3) functions as a transistor, Yang also discloses wherein a conductivity type of the holding transistor is the same as a conductivity type of the driving transistor, see Paras 0071-0072.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a light emitting device taught by Tamura by applying the teaching of Yang to include a drive transistor implemented by using different types of transistors, for example, n-type or p-type thin-film transistors (TFTs) and both of the variable capacitors (formed as a holding transistor) may be TFT-based metal-insulator-semiconductor (MIS) capacitors constructed by connecting a source and a drain of n-type or p-type TFTs, the stability of the drain-to-source current in the driving phase is improved by using the variable capacitor to generate the compensation voltage so as to compensate for threshold voltage shift of drive transistor, as known technique to yield a predictable result.
Regarding claim 2, Tamura in view Yang teaches the device according to claim 1, wherein the driving transistor is arranged on a path connecting the light emitting element and the switching transistor (fig. 2 and Para 0075, wherein the light emitting control transistor 24 is connected between a power line of the power electrical voltage Vcc and a source electrode of the driving transistor 22, and performs the control of the light emitting/non-light emitting of the organic EL element 21, Tamura).
Regarding claim 3, Tamura in view Yang teaches the device according to claim 1, wherein a threshold voltage of the holding transistor is lower than a threshold voltage of the driving transistor (Paras 0068, 0073 and 0077, Yang).
Regarding claim 5, Tamura in view Yang teaches the device according to claim 3, wherein a conductivity type of the gate of the holding transistor is different from a conductivity type of the gate of the driving transistor (Paras 0073 and 0077, Yang).
Regarding claim 8, Tamura in view Yang teaches the device according to claim 1, further comprising a first capacitive element connecting the gate of the driving transistor and the source of the driving transistor (fig. 2, a capacitor 26 and Para 0076, Tamura).
Regarding claim 9, Tamura in view Yang teaches the device according to claim 1, further comprising a second capacitive element connecting the source of the driving transistor and a power supply line (fig. 2, a capacitor 27 and Para 0076, Tamura).
Regarding claim 10, Tamura in view Yang teaches the device according to claim 1, further comprising an initialization transistor arranged on a path connecting a drain of the driving transistor and a power supply line (fig. 2, Transistor 25 and Para 0075, Tamura).
Regarding claim 11, Tamura in view Yang teaches the device according to claim 10, wherein the switching transistor, the holding transistor, the driving transistor, and the initialization transistor are formed in a same active region (fig. 4 and Paras 0110-0115, Tamura).
Regarding claim 13, Tamura in view Yang teaches a display device comprising a light emitting device according to claim 1, and an active element connected to the light emitting device (Para 0073, Tamura).
Regarding claim 14, Tamura in view Yang teaches a photoelectric conversion device comprising (1) an optical unit including a plurality of lenses, (2) an image sensor configured to receive light having passed through the optical unit, and (3) a display unit configured to display an image, wherein the display unit displays an image captured by the image sensor, and includes a light emitting device according to claim 1 (figs 15A/B and Paras 0200-0202, Tamura).
Regarding claim 18, Tamura in view Yang teaches the device according to claim 1, wherein a back gate of the holding transistor and a source of the switching transistor are connected to a same power supply line (fig. 2 and Para 0074, wherein the light emitting control transistor 24 have a four-terminal configuration of Source/Gate/Drain/Back Gate. A power electrical voltage Vcc is applied to the back gate of the light emitting control transistor 24. The combination of the retentive capacitance 26 and the auxiliary capacitance 27 and Para 0076 which function as a holding transistor and Tamura in view Yang disclosed a variable capacitor (T.sub.3) functions as a transistor (figs 2, 26, Paras 0072 and 0133, Yang). In addition, the same motivation is used as the rejection in claim 1.
Claim(s) 4 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura (US 2019/0123124), in view of Yang (US 2015/0084538), and further in view of Tsuboi (US 2020/0126481).
Regarding claim 4, Tamura in view Yang teaches device according to claim 3, but Tamura in view Yang does not expressly disclose wherein a channel concentration of the holding transistor is higher than a channel concentration of the driving transistor.
However, Tsuboi discloses wherein a channel concentration of the holding transistor is higher than a channel concentration of the driving transistor, see fig. 4 and Paras 0042-046.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a light emitting device taught by Tamura in view Yang by applying the teaching of Tsuboi wherein an impurity concentration of the channel region of a driving transistor approaches “0”, the more that variation in the amount of current can be suppressed and the impurity concentration of the channel region of the driving transistor may be lower than the impurity concentration of the well. For example, the impurity concentration of the channel region of the driving transistor may be lower than the impurity concentration of the N-type channel region of the writing transistor, as known technique to yield a predictable result.
Regarding claim 6, Tamura in view Yang and in view of Tsuboi teaches the device according to claim 1, wherein the switching transistor, the holding transistor, and the driving transistor are formed in a same active region (fig. 4 and Paras 0041, Tsuboi).
Regarding claim 7, Tamura in view Yang and in view of Tsuboi teaches the device according to claim 1, wherein the holding transistor and the driving transistor are formed on different semiconductor substrates (fig. 4 and Paras 0041, Tsuboi).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura (US 2019/0123124), in view of Yang (US 2015/0084538), and further in view of Tsuboi (US 2020/0143741), hereinafter “Tsuboi 41”.
Regarding claim 15, Tamura in view Yang does not expressly disclose an electronic apparatus comprising a housing provided with a display unit, and a communication unit provided in the housing and configured to perform external communication, wherein the display unit includes a light emitting device according to claim 1.
However, “Tsuboi 41” disclose an electronic apparatus comprising a housing provided with a display unit, and a communication unit provided in the housing and configured to perform external communication, wherein the display unit includes a light emitting device according to claim 1, see 22B and Para 0117.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a light emitting device taught by Tamura in view Yang by applying the teaching of “Tsuboi 41” to include An electronic apparatus includes a display unit , an operation unit, and a housing. The housing may include a communication unit, as known technique to yield a predictable result.
Regarding claim 16, Tamura in view Yang does not expressly disclose an illumination device comprising a light source, and at least one of a light diffusing unit and an optical film, wherein the light source includes a light emitting device according to claim 1.
However, “Tsuboi 41” disclose an illumination device comprising a light source, and at least one of a light diffusing unit and an optical film, wherein the light source includes a light emitting device according to claim 1, see 24A and Paras 0122-0123.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a light emitting device taught by Tamura in view Yang by applying the teaching of “Tsuboi 41” to include an illumination device may include a housing, a light source, an optical film , and a light diffusion unit, The light source may be the display device including the organic light-emitting element, as known technique to yield a predictable result.
Regarding claim 17, Tamura in view Yang does not expressly disclose a moving body comprising a main body, and a lighting appliance provided in the main body, wherein the lighting appliance includes a light emitting device according to claim 1.
However, “Tsuboi 41”disclose a moving body comprising a main body, and a lighting appliance provided in the main body, wherein the lighting appliance includes a light emitting device according to claim 1, see 24B and Paras 0125-0128.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a light emitting device taught by Tamura in view Yang by applying the teaching of “Tsuboi 41” to include a moving body may include a body and a lighting unit provided in the body. The lighting unit includes the organic light-emitting element, as known technique to yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu (US 10,783,830), relates to design and operation of electronic circuits for delivering electrical current to an element in a display device, such as for example to an organic light-emitting diode (OLED) in the pixel of an active matrix OLED (AMOLED) display device.
Enomoto (US 2012/0086845), relates to a rear radiation type solid-state imaging device, a method of manufacturing the solid-state imaging device, and an electronic apparatus using the solid-state imaging device.
Rao (US 2006/0049464), relates to all semiconductor devices and systems. Particularly it applies to diffused diodes, avalanche diodes, Schottky devices, power MOS transistors, JFET's, RF bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), varactors, digital VLSI, mixed signal circuits and sensor devices including camera ICs employing CCD (Charge Coupled Device) as well as CMOS technologies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.E/Examiner, Art Unit 2625 5/2/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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