DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/11/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0143722) in view of Yanagisawa (2014/0176844).
Regarding claims 1 and 12, Lee teaches A display panel, comprising:
a plurality of pixel units arranged in array (Fig. 6 pixels PX),
a plurality of data lines, connected to the plurality of pixel units(Fig. 6 data lines 171);
a crack detection line (Fig. 6 crack detection lines M1 and M2),
a crack detection circuit, connected to the plurality of data lines and the crack detection line (test controller 700’ [0037]),
a first test signal line (test voltage line TVL),
a first control signal line (Figs. 6 and 8 DCL),
a lighting test circuit ([0044-0045] test controller 700 provides light test signals to data lines),
a second test signal line (Fig. 8 test signal lines M3-M6 connected to respective test pads [0090-0092], and wherein the crack detection line is connected between the crack detection circuit and the first test signal line or the crack detection line is connected between the crack detection circuit and the first control signal line (Fig. 6 crack detection line M1 and M2 are connected to circuit 700’ which is also connected to control signal line DCL); and although Lee teaches the limitations as discussed above, he fails to teach
a second control signal line, wherein the lighting test circuit is connected to the plurality of data lines and is configured to be turned on in response to a signal on the second control signal line, to transmit a test signal on the second test signal line to the plurality of data lines.
However in the field of manufacturing a device to detect a crack in the device, Yanagisawa teaches a first control line of crack inspection unit 20 is connected between TG3 and TG4 and a second control signal line (Fig. 2 gate control line connected between TG1 and TG2) , wherein the lighting test circuit (Fig. 2 light inspection switching transistor unit 10 disposed on IC driver 40) is connected to the plurality of data lines (Fig. 2 video signal lines 50 [0013])and is configured to be turned on in response to a signal on the second control signal line, to transmit a test signal on the second test signal line to the plurality of data lines ([0014][0030]).
Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lee with the method of control signal structure as taught by Yanagisawa. This combination would provide a system that improve a method of simultaneously performing crack detection and lighting inspection as taught by Yanagisawa [0017].
Regarding claim 6, Lee teaches a display region and a non-display region disposed around at least part of the display region, wherein the crack detection circuit (test controller 700’) and the crack detection line (crack detection line M1 and M2) are located in at least part of the non-display region, and the crack detection line is disposed around the display region (Fig. 6 M1 and M2 disposed around display);
wherein the display panel further comprises a data connection line (Fig. 6 part of data line that extends from display region to non-display region connecting to test controller 700’); wherein the data connection line, the first test signal line (TVL), the second test signal line (test signal lines M3-M6), the first control signal line (DCL) are located in the non-display region(Fig. 6 shows all elements listed above disposed outside the pixel region); and the plurality of pixel units are located in the display region (Fig. 6 Pixel PX), and emitted colors of a plurality of pixel units connected to a same data line of the plurality of data lines are the same([0032]) and Yanagisawa teaches the second control signal line located in the non-display region (Fig. 2 gate control line connected between TG1 and TG2).
Regarding claim 7, Lee teaches wherein the non-display region further comprises a first test pad (Fig. 6 test pad P1) and a first control pad (Fig. 6 control pad P3) , the first test signal line is connected to the first test pad (Fig. 6 TVL is connect to pad P1), and the first control signal line is connected to the first control pad (Fig. 6 DCL is connected to test pad P3) ;the non-display region further comprises a second test pad (Fig. 6 pad P2), the second test signal line is connected to the second test pad(Figs. 6 M4 and M6 are connected to test pad P2) , however Yanagisawa teaches a second control pad (Fig. 2 TG1 and TG2) and the second control signal line is connected to the second control pad (Fig. 2 gate control wiring for light inspecting unit 10 connected to TG1 and TG2).
Regarding claim 9, Yanagisawa teaches wherein the and the lighting test circuit is connected to the plurality of data lines through the data connection line (Fig. 2 video signal lines that extend from display region to non-display region); and the lighting test circuit comprises a third switch (Fig. 2 switch unit 70 connected to light inspection unit 10), the third switch comprises a third transistor(Fig. 2 unit 70), a gate of the third transistor is connected to the second control signal line, a first electrode of the third transistor is connected to the second test signal line, and a second electrode of the third transistor is connected to the data connection line (Fig. 2 unit 70 is connected to data line extended into the non-display region, connected first and second control line when test and detection methods are activated).
Regarding claim 11, Yanagisawa teaches first control pad connected to the first control signal line, wherein a first control signal applied to the first control pad is a direct current voltage signal (Fig. control line wiring for crack inspection unit 20 connected to control pad TG3 and TG4);
the display panel further comprises a bonding region (terminal region 120 where drive IC is bonded), a third control pad is disposed in the bonding region (Fig. 2 control pad RGB), and the third control pad is connected to the first control signal line (Connected during crack detection activation);
the first control signal line is connected to the first control pad Fig. control line wiring for crack inspection unit 20 connected to control pad TG3 and TG4);; a first test signal on the first test signal line is a fixed voltage signal ([0039]); a size of the first control pad is greater than a size of the third control pad; and the third control pad is connected to the first control signal line through a third control signal line (Fig. 2).
Regarding claim 13, Lee in view of Yanagisawa teach the limitations according to the display panel of claim 1 Yanagisawa teaches a display device comprising a driver chip and the display panel (driver IC 40).
Regarding claim 14, Yanagisawa teaches wherein the display panel comprises a bonding region, a third control pad is disposed in the bonding region, the driver chip is located in the bonding region, and a signal output pad on the driver chip is bonded and connected to the third control pad (Fig. 2 shows third control pad S connected to driver chip 40 in bonding region.).
Regarding claim 15, Yanagisawa teaches a flexible printed circuit (Fig. 7 flexible wiring substrate 110), the display panel further comprises a first test pad (with reference back to Fig. 2 terminal area 120 comprises first test pad TG1 and TG2), and the flexible printed circuit is configured to be bonded and connected to the first test pad (Fig. 7 shows flexible wiring substrate 110 connected to bonding to terminal area 120).
Allowable Subject Matter
Claims 2-5 and 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is indicated allowable based on the structure of the crack detection circuit.
Claim 8 is indicated allowable based on the structure of the second test pad.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00.
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/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
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