DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priorities
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0003435, filed on 01/09/2024.
Information Disclosure Statement
The information disclosure statements filed 10/28/2024 has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (US Pub. 2024/0105091 A1).
Regarding claim 1; Liu teaches a gate driver (a gate driving circuit 200, Fig.10, para. [0257]) comprising:
[AltContent: textbox (Second scan signal)][AltContent: textbox (Fourth scan signal)][AltContent: arrow][AltContent: textbox (Third scan signal)][AltContent: arrow][AltContent: arrow][AltContent: textbox (First scan signal)][AltContent: arrow]
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(Fig.16 of Liu reproduced)
a level shifter (a mode control circuit 210, Fig.10) configured to output first-mode gate clocks in a normal scan rate mode (Fig.16, para. [0257], the mode control circuit 210 is configured to receive initial clock signals clk1-clk8 and generate clock signals CLK1-CLK8 according to a control signal SW. For example, Fig.16, the mode control circuit 210 may be configured to output clock signals CLK1-CLK8 in an 8K resolution display mode in a first period P1) and output second-mode gate clocks in a high scan rate mode (Fig.16, in a second period P2, the mode control circuit 210 may be configured to output clock signals CLK1-CLK8 in an 4K resolution display mode in which two adjacent gate lines are scanned at the same time (i.e., dual line gate scanning scheme)) having a scan rate greater than the normal scan rate mode (Fig.16, in the 4K resolution display mode, the gate lines are scanned in a higher scanning rate than the 8K resolution display mode); and
a gate shifter register (shift registers GOA1-GOA13, Fig.10) configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode (Figs.10 and 16, para. [0259], in the first period P1, the shift registers are configured to output gate signals in the 8K resolution mode in response to clock signals CLK1-CLK8) and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode (Figs.10 and 16, para. [0259], in the second period P2, the shift registers are configured to output gate signals in the 4K resolution mode in response to clock signals CLK1-CLK8),
wherein adjacent gate clocks of the first-mode gate clocks have a delay difference equal to one horizontal period (Fig.16, para. [0280], each clock signal has a length of 4 horizontal periods (i.e., 4H). In the first period P1 (i.e., 8K resolution display mode), adjacent clock signals are shifted by one horizontal period (1H)),
the second-mode gate clocks comprise first, second, third, and fourth gate clocks where a phase is sequentially shifted (Fig.16, in the second period P2, a phase of clock signals CLK1-CLK8 is sequentially shifted), and the first and third gate clocks have a delay difference equal to the one horizontal period (Fig.16, in the second period P2, the phases of CLK1 and CLK3 have one horizontal period difference (i.e., shifted by 1H), the first and second gate clocks have a delay difference that is less than the one horizontal period (Fig.16, in the second period P2, phases of clock signals CLK1 and CLK2 are substantially the same), and the third and fourth gate clocks have a delay difference that is less than the one horizontal period (Fig.16, in the second period P2, phases of clock signals CLK3 and CLK4 are substantially the same).
Regarding claim 7; Liu teaches a display device (Fig.1, a display device) comprising:
a display panel (a display panel, Fig.1) including a plurality of pixels (pixels PXL), a plurality of gate lines connected to the plurality of pixels (Fig.1, a plurality of gate lines G1-GX connected to pixels PXL), and a plurality of data lines connected to the plurality of pixels (para. [0003], data signal is applied to pixels PXL through data lines);
a gate driver (a gate driving circuit 200, Fig.10) configured to drive the plurality of gate lines (Fig.10); and a data driver configured to drive the plurality of data lines (para. [0003], the display panel inherently comprises a data driver for supplying data signal to the plurality of pixels through a plurality of data lines), wherein the gate driver comprises: a level shifter configured to output first-mode gate clocks in a normal scan rate mode and output second-mode gate clocks in a high scan rate mode having a scan rate greater than the normal scan rate mode; and a gate shifter register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks to the plurality of gate lines in the normal scan rate mode and output high scan rate scan signals synchronized with the second-mode gate clocks to the plurality of gate lines in the high scan rate mode, wherein adjacent gate clocks of the first-mode gate clocks have a delay difference equal to one horizontal period, the second-mode gate clocks comprise first, second, third, and fourth gate clocks where a phase is sequentially shifted, and the first and third gate clocks have a delay difference equal to the one horizontal period, the first and second gate clocks have a delay difference that is less than the one horizontal period, and the third and fourth gate clocks have a delay difference that is less than the one horizontal period (similar to the analysis of claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Pub. 2024/0105091 A1) in view of Park et al. (US Pub. 2007/0262310 A1).
Regarding claim 2; Liu teaches the gate driver of claim 1 as discussed above. Liu teaches a rising edge of the third gate clock is delayed in phase by the one horizontal period compared to a rising edge of the first gate clock (Fig.16, in the second period P2, a rising edge of a third scan signal is delayed by one horizontal period compared to a rising edge of the first scan signal).
Liu does not teach wherein, in an odd-numbered frame of the high scan rate mode, a rising edge of the second gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the first gate clock, and a rising edge of the fourth gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the third gate clock.
Park teaches wherein, in an odd-numbered frame of the high scan rate mode (Fig.6A, para. [0050] in an odd-numbered frame), a rising edge of the second gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the first gate clock, and a rising edge of the fourth gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the third gate clock (para. [0050], during the odd-numbered frame, the gate signals on the odd-numbered gate lines (e.g., GL1, GL3, GL2-1) have the same phase as the horizontal sync signal, but the gate signals on the even-numbered gate lines (e.g., GL2, GL4, . . . , GLn) have phases that are advanced by “alpha” versus the horizontal sync signals. In other words, a rising edge of the gate signal GL2 would be delayed by a time period “alpha” less than one horizontal period compared to a rising edge of the first gate signal GL1. Similarly, a rising edge of gate signal GL4 would be delayed by a time period “alpha” less than one horizontal period compared to a rising edge of gate signal GL3).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Liu to include the teaching of Park of shifting odd-numbered gate signals by a time period “alpha” less than one horizontal period compared to even-numbered gate signals. The motivation would have been in order to secure sufficient writing time to store video signals at a high frame frequency (Park, para. [0003]).
Regarding claim 8; Liu teaches the display device of claim 7 as discussed above. The limitation of claim 8 is substantially similar to claim 2. Accordingly, claim 8 is rejected based on the same analysis as claim 2.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Pub. 2024/0105091 A1) in view of Byun et al. (US Pub. 2011/0157132 A1).
Regarding claim 4; Liu teaches the gate driver of claim 1 as discussed above. Liu does not teach each of the first, second, third, and fourth gate clocks comprises at least one inflection point in a rising edge or a falling edge thereof.
Byun teaches each of the first, second, third, and fourth gate clocks comprises at least one inflection point in a rising edge or a falling edge thereof (Figs. 8, 13, 16C, and 16D; para. [0069], a rising edge of a gate pulse has an inflection point at a boundary between time B and time C (Fig.8)).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the gate driving circuit of Liu to include the teaching of Byun of providing a gate pulse having an inflection point. The motivation would have been in order to reduce power consumption and kickback voltage (Byun, para. [0012]).
Regarding claim 10; Liu teaches the display device of claim 7 as discussed above. The limitation of claim 10 is substantially similar to claim 4. Accordingly, claim 10 is rejected based on the same analysis as claim 4.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Pub. 2024/0105091 A1) in view of Byun et al. (US Pub. 2011/0157132 A1) as applied to claims 4 and 10 above; further in view of Park et al. (US Pub. 2007/0262310 A1).
Regarding claim 5; Liu in view of Byun teaches the gate driver of claim 4 as discussed above. Liu teaches a rising edge of the third gate clock is delayed in phase by the one horizontal period compared to a rising edge of the first gate clock (Fig.16, in the second period P2, a rising edge of a third scan signal is delayed by one horizontal period compared to a rising edge of the first scan signal).
Liu does not teach wherein, in an odd-numbered frame of the high scan rate mode, a rising edge of the second gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the first gate clock, and a rising edge of the fourth gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the third gate clock.
Park teaches wherein, in an odd-numbered frame of the high scan rate mode (Fig.6A, para. [0050] in an odd-numbered frame), a rising edge of the second gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the first gate clock, and a rising edge of the fourth gate clock is delayed in phase by a time period less than the one horizontal period compared to the rising edge of the third gate clock (para. [0050], during the odd-numbered frame, the gate signals on the odd-numbered gate lines (e.g., GL1, GL3, GL2-1) have the same phase as the horizontal sync signal, but the gate signals on the even-numbered gate lines (e.g., GL2, GL4, . . . , GLn) have phases that are advanced by “alpha” versus the horizontal sync signals. In other words, a rising edge of the gate signal GL2 would be delayed by a time period “alpha” less than one horizontal period compared to a rising edge of the first gate signal GL1. Similarly, a rising edge of gate signal GL4 would be delayed by a time period “alpha” less than one horizontal period compared to a rising edge of gate signal GL3).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Liu to include the teaching of Park of shifting odd-numbered gate signals by a time period “alpha” less than one horizontal period compared to even-numbered gate signals. The motivation would have been in order to secure sufficient writing time to store video signals at a high frame frequency (Park, para. [0003]).
Regarding claim 11; Liu in view of Byun teaches the display device of claim 10 as discussed above. The limitation of claim 11 is substantially similar to claim 5. Accordingly, claim 11 is rejected based on the same analysis as claim 5.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Pub. 2024/0105091 A1) in view of Ma et al. (US Pub. 2024/0321230 A1).
Regarding claim 13; Liu teaches the display device of claim 7 as discussed above. Liu does not explicitly teach in the normal scan rate mode, the data driver is configured to synchronize an image data voltage having a first resolution with the normal scan rate scan signals to output to the plurality of data lines, and in the high scan rate mode, the data driver is configured to synchronize an image data voltage having a second resolution which is less than the first resolution with the high scan rate scan signals to output to the plurality of data lines.
Ma teaches in the normal scan rate mode (Figs. 5 and 10, a normal (sequentially) scanning mode), the data driver (a data drive circuit, Figs. 1-4) is configured to synchronize an image data voltage having a first resolution with the normal scan rate scan signals to output to the plurality of data lines (para. [0011], the data drive circuit is configured to, in the frame scan cycle, write a first data signal to the first sub-pixel through the representative data line, and simultaneously write a second data signal or a third data signal to the second sub-pixel and the third sub-pixel through the representative data line), and in the high scan rate mode (Figs. 6 and 9, a dual line gate mode), the data driver is configured to synchronize an image data voltage having a second resolution which is less than the first resolution with the high scan rate scan signals to output to the plurality of data lines (para. [0011]).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Liu to include the teaching of Ma of providing a data drive circuit for synchronously applying image data voltage to a plurality of pixels through a plurality of data lines in a normal scanning mode and a dual line gate mode. The motivation would have been in order to supply data voltage to pixels for displaying images.
Regarding claim 14; Liu in view of Ma teaches the display device of claim 13 as discussed above. Liu does not teach in the high scan rate mode, a first pixel and a second pixel which are connected to a same data line and are disposed adjacent to each other are charged with a same image data voltage.
Ma teaches in the high scan rate mode, a first pixel and a second pixel which are connected to a same data line and are disposed adjacent to each other are charged with a same image data voltage (Figs. 4 and 12, two adjacent pixels on a same row are commonly connected to a same data line).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Liu to include the teaching of Ma of connecting two adjacent pixels on the same row to the same data line. The motivation would have been in order to reduce a number of data lines.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Pub. 2024/0105091 A1) in view of Ma et al. (US Pub. 2024/0321230 A1) as applied to claim 14 above; further in view of Kim (US Pub. 2006/0290644 A1).
Regarding claim 15; Liu in view of Ma teaches the display device of claim 14 as discussed above. Liu and Ma do not teach in an odd-numbered frame of the high scan rate mode, a data charge time of the first pixel is longer than a data charge time of the second pixel, and in an even-numbered frame of the high scan rate mode, a data charge time of the first pixel is shorter than a data charge time of the second pixel.
Kim teaches in an odd-numbered frame, a data charge time of the first pixel is longer than a data charge time of the second pixel (Fig.5A, para. [0036], in an odd-numbered frame, a time period T1 of first gate signal GL1 is longer than a time period T2 of a second gate signal GL2. It is understood that a data charge time would be corresponding to a length of gate signal), and in an even-numbered frame, a data charge time of the first pixel is shorter than a data charge time of the second pixel (Fig.5B, para. [0037], in an even-numbered frame, the time period T1 of the first gate signal GL1 is shorter than the time period T2 of the second gate signal GL2).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Liu in view of Ma to include the teaching of Kim of adjusting lengths of gate signals in an odd frame and even frame. The motivation would have been in order to improve a charge property (Kim, para. [0013]).
Claims 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 2022/0208105 A1) in view of Chang (US Pub. 2008/0224984 A1).
Regarding claim 16; Lee teaches a gate driver (a gate driver, Fig.17) comprising:
a level shifter (a level shifter 300, Fig.17) configured to output gate clocks (Fig.17, para. [0322], the level shifter 300 is configured to output gate clock CLK1-CLK4); and
a gate shifter register (a gate driving circuit 130, Fig.17) configured to output scan signals based on the gate clocks (the gate driving circuit 130 is configured to output gate signals GL1-GL4), the gate shifter register including a plurality of stages (control circuits 500, Fig. 18), a stage of the plurality of stages including a plurality of output circuits (Fig.18, four buffer circuit GBUF1-GBUF4), the plurality of output circuits including a first output circuit (e.g., GBUF1, Fig.18) and a second output circuit (e.g., GBUF2, Fig.18) configured to output a first scan signal (e.g., Vgout1, Fig.18) and a second scan signal (e.g., Vgout2, Fig.18), respectively (Fig.18).
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(Fig.18 of Lee reproduced)
Lee does not teach wherein in a first frame of a first scan rate mode the second scan signal is later than the first scan signal by a first delay time, and in a second frame subsequent to the first frame in the first scan rate mode, the second scan signal is earlier than the first scan signal.
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(Fig.7 of Chang reproduced)
Chang teaches wherein in a first frame (e.g., a frame (4N+1), Figs. 7 and 10) of a first scan rate mode the second scan signal is later than the first scan signal by a first delay time (Figs. 7 and 10, in a frame (4N+1), a second gate signal G2 is later than a first gate signal G1 by a delayed time), and in a second frame (e.g., frame (4N+2)) subsequent to the first frame in the first scan rate mode (Figs.7 and 10), the second scan signal is earlier than the first scan signal (Figs. 7 and 10, in a subsequent frame (4N+2), the second gate signal G2 is earlier than the first gate signal G1).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Lee to include the teaching of Kim of reversely scanning two adjacent gate lines in a subsequent frame. The motivation would have been in order to mitigate a phenomenon of vertical bright and dim stripes derived from uneven brightness and dimness (Chang, para. [0035]).
Regarding claim 17; Lee in view of Chang teaches the gate driver of claim 16 as discussed above. Lee further teaches the first output circuit and the second output circuit share a same Q node and a same QB node (Fig.18, the GBUF1 and GBUF2 share a same Q node and a same QB node of the control circuit 500).
Regarding claim 18; Lee in view of Chang teaches the gate driver of claim 17 as discussed above. Lee further teaches the first output circuit (Fig.18, GBUF1) includes a first pull-up transistor (a first pull-up transistor Tu1, Fig.18) and a first pull-down transistor (a first pull-down transistor Td1, Fig.18); the second output circuit (Fig.18, GBUF2) includes a second pull-up transistor (a second pull-up transistor Tu2, Fig.18) and a second pull-down transistor (a second pull-down transistor Td2, Fig.18); a gate of the first pull-up transistor and a gate of the second pull-up transistor are connected to the Q node (see Fig.18); and a gate of the first pull-down transistor and a gate of the second pull-down transistor are connected to the QB node (Fig.18).
Regarding claim 20; Lee in view of Chang teaches the gate driver of claim 16 as discussed above. Lee further teaches the plurality of output circuits of the stage include a third output circuit (GBUF3, Fig.18) and a fourth output circuit (GBUF4, Fig.18) configured to output a third scan signal (Vgout3) and a fourth scan signal (Vgout4), respectively (Fig.18).
Lee does not teach wherein in the first frame of the first scan rate mode, the third scan signal is later than the second scan signal and the fourth scan signal is later than the third scan signal; and wherein in the second frame subsequent to the first frame in the first scan rate mode, the third scan signal is later than both the first scan signal and the second scan signal, and the fourth scan signal is earlier than the third scan signal.
Chang teaches wherein in the first frame (Figs. 7 and 10, e.g., frame (4N+1)) of the first scan rate mode, the third scan signal (a third scan signal G3) is later than the second scan signal (in the frame (4N+1), the third scan signal G3 is later than the second scan signal G2) and the fourth scan signal is later than the third scan signal (in the frame (4N+1), the fourth scan signal G4 is later than the third scan signal G3); and wherein in the second frame (Figs. 7 and 10, e.g., frame (4N+2)) subsequent to the first frame in the first scan rate mode (Figs. 7 and 10), the third scan signal is later than both the first scan signal and the second scan signal (in the frame (4N+2), the third scan signal G3 is later than the first scan signal G1 and the second scan signal G2), and the fourth scan signal is earlier than the third scan signal (In the frame (4N+2), the fourth scan signal G4 is earlier than the third scan signal G3).
The motivation is the same as the rejection of claim 16.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 2022/0208105 A1) in view of Chang (US Pub. 2008/0224984 A1) as applied to claim 16 above; further in view of Su et al. (US Pub. 2023/0401987 A1).
Regarding claim 19; Lee in view of Chang teaches the gate driver of claim 16 as discussed above. Lee and Chang do not teach in a second scan rate mode, the second scan signal is later than the first scan signal by a second delay time, the second delay time greater than the first delay time.
Su teaches in a second scan rate mode, the second scan signal is later than the first scan signal by a second delay time, the second delay time greater than the first delay time (Para. [0026], Fig.3A, Su discloses a first scan rate mode in which scan signals are sequentially shifted by one horizontal period (1H). In other words, in the first scan rate mode, a scan signal (e.g., OUT3) is later than a previous scan signal (e.g., OUT2) by one horizontal period (1H). In Fig.3B, Su further discloses a second scan rate mode in which two adjacent gate lines are simultaneously scanned. In the second scan rate mode, a scan signal (e.g., OUT3) is later than a previous scan signal (e.g., OUT2) by two horizontal periods (2H)).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display panel of Lee in view of Chang to include the teaching of Su of providing two scan rate modes (i.e., row-by-row scanning mode and two-rows by two-rows scanning mode). The motivation would have been in order to implement full-resolution display (Su, para. [0070]).
Allowable Subject Matter
Claims 3, 6, 9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach in “in an even-numbered frame of the high scan rate mode, a rising edge of the second gate clock is ahead in phase by a time period less than the one horizontal period compared to the rising edge of the first gate clock, and a rising edge of the fourth gate clock is ahead in phase by a time period less than the one horizontal period compared to the rising edge of the third gate clock” as recited in claims 3, 6, 9, and 12.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623