03Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 11-12, 16, and 19-20. Claim 2 is cancelled. Claims 1 and 3-20 are currently under review.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-19 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to claim 20, filed November 26, 2025 have been fully considered but they are not persuasive. The Applicant argues on the bottom of page 11 of the remarks that claim 20 discloses a specific configuration not taught by Lee, namely “increase a power level supplied to at least one output buffer among the output buffers” and argues on page 12 of the remarks that Lee teaches a multiplexer controller outputs control signals that overlap with each other to reduce power consumption by reducing the overall number of transitions. The Office disagrees. Lee teaches in paragraph 5 that “when reversing of a voltage level of control signals (e.g., transition) very frequently over a short period of time, a circuit section generating the control signal consumes a large amount of power”. Lee shows in figure 6, that one voltage signal is reversed in t1, two voltage signals are reversed in t2, and one voltage signal is reversed in t3, therefore since power consumption is increased during transitions, an increase in power level is supplied to at least one output buffer among the output buffers occurs at t2 even though overall power consumption is reduced by control signals overlapping with each other. Review of Applicant’s specification indicates that the invention is directed to enhancing slew rate to improve responsiveness and reduce power consumption (see ¶5). Paragraph 90 of the specification indicates that “during the overlapping period of the mux control signals MUX1 to MUX3, the slew rate of the data voltage output from the output buffer 341 and 342 increases, thereby deteriorating performance of the output buffers 341 and 342”, therefore paragraphs 99-100 indicate adjusting the magnitude of bias current depending on power consumption can reduce power consumption. Paragraph 101 indicates “Therefore, by dynamically controlling or adjusting the power consumption of the output buffers 341 and 342, it is possible to change and improve the slew rate of the output buffers 341 and 342 when desirable, while also reducing power consumption”, where the adjusting of the power consumption is thru adjusting bias current, which is not mentioned in claim 20.
Claim Objections
Claim 12 is objected to because of the following informalities: typographic errors. Appropriate correction is required.
Claim 12, line 15: “consumption by increasing [[a]]the bias current when the turn-on periods of at least”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Pub. No.: US 2018/0151137 A1) hereinafter referred to as Lee.
With respect to Claim 20, Lee discloses a display device (fig. 1; ¶25), comprising: a display panel (fig. 1, item 100; ¶26) including a plurality of subpixels (figs. 1 & 4, item P; ¶34), a plurality of data lines (figs. 1 & 4, items DL1, DL2, … DL3m) and a plurality of gate lines (figs. 1 & 4, items GL1, GL2, …, GLn); a data driver (fig. 1, item 400; ¶30-31) configured to supply data voltages to the plurality of data lines via output buffers (figs. 3, item 450; fig. 4, items BUF1, BUF2; ¶31; ¶36); and a multiplexer (fig. 1, item 500; ¶32) connected between the data driver and the plurality of data lines, the multiplexer being configured to receive a plurality of mux control signals and supply the data voltages to the plurality of data lines based on the plurality of mux control signals (¶37-38), wherein the data driver is further configured to: in response to transitioning from a first state including only one of the plurality of mux control signals being at a turn on level while remaining mux control signals among the plurality of mux control signals are at a turn-off level (fig. 6, t3 in 1st H: first state) to a second state including at least two of the plurality of mux control signals having the turn-on level at a same time (fig. 6, t1 in 2nd H: second state), increase a power level supplied to at least one output buffer among the output buffers (¶5; ¶42-43, power level is increased since more least two mux control signals are supplied to turn on the transistor in MUX).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Tsuchi (Pub. No.: US 2024/0321169 A1).
With respect to Claim 1, Lee teaches a display device (fig. 1; ¶25), comprising: a display panel (fig. 1, item 100; ¶26) including a plurality of subpixels (figs. 1 & 4, item P; ¶34); a data driver (fig. 1, item 400; ¶30-31) configured to supply a data voltage to the plurality of subpixels through a plurality of data lines; and a multiplexer (fig. 1, item 500; ¶32) connected between the data driver and the plurality of data lines (fig. 1, item DL, DL2, DL3 etc), the multiplexer including a plurality of switching elements (fig. 4, items M1, M2, M3, M4, M5, and M6) controlled by a plurality of mux control signals (fig. 4, item Mux1, Mux2, Mux3: plurality of mux control signals; ¶38), wherein a power consumption mode of the data driver is configured to change based on whether turn-on periods of the plurality of mux control signals overlap with each other (fig. 6; ¶45, overlap exists in t1 and t2 of 1st H, none in t3 of 1st H, therefore power consumption changes, when fewer control signal are high, there is less power consumption; ¶5; ¶42-43).
Lee does not mention wherein the data driver is configured to temporarily increase power consumption by increasing a bias current when the turn-on periods of at least two of the plurality of mux control signals overlap with each other.
Tsuchi teaches a display device (fig. 8, item 600; ¶135), comprising: a display panel (fig. 8, item 150; ¶136) including a plurality of subpixels (fig. 8, item 154; ¶136); a data driver (fig. 8, item 120; ¶136; ¶140) configured to supply a data voltage to the plurality of subpixels through a plurality of data lines (¶139-140); and a multiplexer (fig. 8, item MX1 … MXk; ¶139) connected between the data driver and the plurality of data lines, the multiplexer including a plurality of switching elements (fig. 8, item SW1, SW2, SW3) controlled by a plurality of mux control signals (¶140, “The switches SW1 to SW3 are sequentially and selectively set to be ON according to data line selection signals Sa, Sb, Sc supplied from the data driver 120”), wherein a power consumption mode of the data driver is configured to change based on turn-on periods of the plurality of mux control signals (fig. 9; ¶45-47; ¶156-157), and wherein the data driver is configured to temporarily increase power consumption by increasing a bias current of the turn-on periods of at least two of the plurality of mux control signals (fig. 9; ¶156-157, current is only increased temporarily during periods Twr and Twf).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Lee, such that a power consumption mode of the data driver is configured to change based on turn-on periods of the plurality of mux control signals, and wherein the data driver is configured to temporarily increase power consumption by increasing a bias current of the turn-on periods of at least two of the plurality of mux control signals, the combination resulting in wherein the data driver is configured to temporarily increase power consumption by increasing a bias current when the turn-on periods of at least two of the plurality of mux control signals overlap with each other, as taught by Tsuchi so as to reduce power consumption by reducing the average consumed current by the bias part (¶158).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Tsuchi as applied to claim 1 above, and further in view of Oh et al. (Pub. No.: US 2015/0255042 A1) hereinafter referred to as Oh and in view of Oh (Pub. No.: KR20220096085A) hereinafter referred to as Oh2.
With respect to Claim 3, claim 1 is incorporated, Lee discloses wherein the data driver includes: an output buffer (fig. 3, item 450; ¶31, “The output unit 450 may be implemented as an output buffer outputting a data voltage using a low potential voltage GND and a voltage received through a high potential input terminal, as driving voltages”).
Although Lee teaches a calculator (fig. 1, item 600) configured to output a logic signal (logic signal: the level of the mux control signal) at a different levels based on overlapping or non-overlapping of turn-on periods of a plurality of mux control signals (fig. 6; ¶45; ¶55), Lee and Tsuchi combined do not mention that the data driver includes a calculator; a power management circuit configured to output the bias current based on a combination of a power control signal directing the power consumption mode of the data driver and the logic signal output by the calculator.
Oh teaches a data driver (fig. 1, item 12; ¶35), comprising: a register (fig. 1, item 38; ¶60); a latch (fig. 1, item 40) configured to latch image data and output the image data (¶61); a digital to analog converting part (fig. 1, item 44) configured to convert the image data output from the latch into a gamma compensation voltage for generating a data voltage (¶63); a calculator (fig. 1, item 64) configured to output a logic signal at different levels for controlling operations (fig. 1, output PCS to item 60 which affects item 62: power management circuit and outputs OCS to item 45 which affects item 48; ¶67, “the output unit 45 may receive the output control signal OCS from the control logic section 64, and the output control signal OCS may include a source enable signal SOE for driving the output buffer 46 and a switching control signal for the switching operation of the multiplexer 48” – the switching control signal corresponds to a logic signal; ¶76); a power management circuit (fig. 1, items 62 and 33) configured to output a bias value based on a combination of a power control signal directing a power consumption mode (¶73, “The power controller 62 may be configured to output power control signals S1 to S6 to which any one of the bias option data BD and the normal mode select data NPC is applied”) and the logic signal (¶75, “the power control signal S6 provided to the multiplexer 48 may provide a power option for selecting a switching state in which the switching element of the multiplexer 48 is turned off or floated, in order to block the source driving signal OUT of the output buffer 46 from being transmitted to the display pan” – selecting a switching state corresponds to a state having the logic signal); and an output buffer (fig. 1, item 46).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display device of Lee and Tsuchi, such that the data driver comprises: a calculator; and a power management circuit configured to output the bias current based on a combination of a power control signal directing a power consumption mode and the logic signal output by the calculator, as taught by Oh so as to reduce power consumption (¶10).
Lee, Tsuchi, and Oh combined do not explicitly mention an output buffer configured to amplify the data voltage based on the bias current to output an amplified data voltage to one or more of the plurality of data lines.
Oh2 teaches a data driver (fig. 1, item 30; ¶36), comprising: a register (fig. 4, item 113) configured to generate a sampling signal based on a data driving control signal (¶53); a latch (fig. 4, item 32) configured to latch image data and output the image data in response to the sampling signal (¶54); a digital to analog converting part (fig. 4, item 33) configured to convert the image data output from the latch into a gamma compensation voltage for generating a data voltage (¶55); a power management circuit (fig. 4, item 35) configured to output a bias current based on a combination of a power control signal directing a power consumption mode (¶58) and a logic signal (¶44, the logic signal corresponds to control signals to select switching state of the switching elements S1, S2, and S3); and an output buffer (fig. 4, item 34) configured to amplify the data voltage based on the bias current to generate an amplified data voltage (¶62).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display device of Lee, Tsuchi, and Oh, such that an output buffer is configured to amplify the data voltage based on the bias current to output an amplified data voltage to one or more of the plurality of data lines, as taught by Oh so as to improve image quality (¶25).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Tsuchi, in view of Oh, and in view of Oh2.
With respect to Claim 12, Lee teaches a data driver (figs. 1 & 3, item 400; ¶30), comprising: a register (fig. 3, item 410; ¶31, “The register unit 410 samples RGB digital video data bits of the input image using data control signals SSC and SSP provided from the timing controller 200”) configured to generate a sampling signal based on a data driving control signal; a latch (fig. 3, item 420; ¶31, “The first latch 420 samples and latches the digital video data bits according to clocks sequentially provided from the register unit 410, and simultaneously outputs the latched data”) configured to latch image data and output the image data in response to the sampling signal, a digital to analog converter (fig. 3, item 440; ¶31, “the DAC 440 converts video data input from the second latch unit 430 into a gamma compensation voltage GMA to generate an analog video data voltage”) configured to convert the image data, which is a digital signal output from the latch into a gamma compensation voltage, which is an analog signal for generating a data voltage; and an output buffer (fig. 3, item 450; ¶31).
Although Lee teaches a calculator (fig. 1, item 600) configured to output a logic signal (logic signal: the level of the mux control signal) at a different levels based on overlapping or non-overlapping of turn-on periods of a plurality of mux control signals (fig. 6; ¶45; ¶55), Lee does not mention that the data driver includes a calculator; a power management circuit configured to output a bias current based on a combination of a power control signal directing the power consumption mode of the data driver and the logic signal output by the calculator.
Oh teaches a data driver (fig. 1, item 12; ¶35), comprising: a register (fig. 1, item 38; ¶60); a latch (fig. 1, item 40) configured to latch image data and output the image data (¶61); a digital to analog converting part (fig. 1, item 44) configured to convert the image data output from the latch into a gamma compensation voltage for generating a data voltage (¶63); a calculator (fig. 1, item 64) configured to output a logic signal at different levels for controlling operations (fig. 1, output PCS to item 60 which affects item 62: power management circuit and outputs OCS to item 45 which affects item 48; ¶67, “the output unit 45 may receive the output control signal OCS from the control logic section 64, and the output control signal OCS may include a source enable signal SOE for driving the output buffer 46 and a switching control signal for the switching operation of the multiplexer 48” – the switching control signal corresponds to a logic signal; ¶76); a power management circuit (fig. 1, items 62 and 33) configured to output a bias value based on a combination of a power control signal directing a power consumption mode (¶73, “The power controller 62 may be configured to output power control signals S1 to S6 to which any one of the bias option data BD and the normal mode select data NPC is applied”) and the logic signal (¶75, “the power control signal S6 provided to the multiplexer 48 may provide a power option for selecting a switching state in which the switching element of the multiplexer 48 is turned off or floated, in order to block the source driving signal OUT of the output buffer 46 from being transmitted to the display pan” – selecting a switching state corresponds to a state having the logic signal); and an output buffer (fig. 1, item 46).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Lee, such that the data driver comprises: a calculator; and a power management circuit configured to output a bias current based on a combination of a power control signal directing a power consumption mode and the logic signal output by the calculator, as taught by Oh so as to reduce power consumption (¶10).
Lee and Oh combined do not explicitly mention an output buffer configured to amplify the data voltage based on the bias current to output an amplified data voltage to one or more of the plurality of data lines.
Oh2 teaches a data driver (fig. 1, item 30; ¶36), comprising: a register (fig. 4, item 113) configured to generate a sampling signal based on a data driving control signal (¶53); a latch (fig. 4, item 32) configured to latch image data and output the image data in response to the sampling signal (¶54); a digital to analog converting part (fig. 4, item 33) configured to convert the image data output from the latch into a gamma compensation voltage for generating a data voltage (¶55); a power management circuit (fig. 4, item 35) configured to output a bias current based on a combination of a power control signal directing a power consumption mode (¶58) and a logic signal (¶44, the logic signal corresponds to control signals to select switching state of the switching elements S1, S2, and S3); and an output buffer (fig. 4, item 34) configured to amplify the data voltage based on the bias current to generate an amplified data voltage (¶62).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Lee and Oh, such that an output buffer is configured to amplify the data voltage based on the bias current to output an amplified data voltage to one or more of the plurality of data lines, as taught by Oh2 so as to improve image quality (¶25).
Lee, Oh, and Oh2 do not mention wherein the power management circuit is configured to temporarily increase power consumption by increasing a bias current when the turn-on periods of at least two of the plurality of mux control signals overlap with each other.
Tsuchi teaches a display device (fig. 8, item 600; ¶135), comprising: a display panel (fig. 8, item 150; ¶136) including a plurality of subpixels (fig. 8, item 154; ¶136); a data driver (fig. 8, item 120; ¶136; ¶140) configured to supply a data voltage to the plurality of subpixels through a plurality of data lines (¶139-140); and a multiplexer (fig. 8, item MX1 … MXk; ¶139) connected between the data driver and the plurality of data lines, the multiplexer including a plurality of switching elements (fig. 8, item SW1, SW2, SW3) controlled by a plurality of mux control signals (¶140, “The switches SW1 to SW3 are sequentially and selectively set to be ON according to data line selection signals Sa, Sb, Sc supplied from the data driver 120”), wherein a power consumption mode of the data driver is configured to change based on turn-on periods of the plurality of mux control signals (fig. 9; ¶45-47; ¶156-157), and wherein the data driver is configured to temporarily increase power consumption by increasing a bias current of the turn-on periods of at least two of the plurality of mux control signals (fig. 9; ¶156-157, current is only increased temporarily during periods Twr and Twf).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined data driver of Lee, Oh, and Oh2, to incorporated the teachings of Tsuchi, namely that a power consumption mode of the data driver is configured to change based on turn-on periods of the plurality of mux control signals, and wherein the data driver is configured to temporarily increase power consumption by increasing a bias current of the turn-on periods of at least two of the plurality of mux control signals, into the combined power management circuit Lee, Oh, and Oh2 resulting in the power management circuit is configured to temporarily increase power consumption by increasing a bias current when the turn-on periods of at least two of the plurality of mux control signals overlap with each other, as taught by Tsuchi so as to reduce power consumption by reducing the average consumed current by the bias part (¶158).
Allowable Subject Matter
Claims 4-11 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art teaches (1) a display device comprising a calculator, wherein the calculator is further configured to: in response to at least two mux control signals among the plurality of mux control signals being at a turn-on level at a same time, output the logic signal at a first level, and in response to only one mux control signal among the plurality of mux control signals is at the turn-on level while remaining mux control signals among the plurality of mux control signals are at a turn-off level, output the logic signal at a second level different than the first level or (2) a data driver, comprising a calculator, wherein the calculator is further configured to: in response to at least two mux control signals among the plurality of mux control signals being at a turn-on level at a same time, output the logic signal at a first level, and in response to only one mux control signal among the plurality of mux control signals being at the turn-on level while remaining mux control signals among the plurality of mux control signals are at a turn-off level, output the logic signal at a second level different than the first level including all the base limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DONNA V Bocar/Examiner, Art Unit 2621