DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application # 18/928,870 was filed on 10/28/2024.
Claims 1-20 are subject to examination.
An IDS filed on 8/1/2025 & 1/22/2025 has been fully considered and entered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, 12-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anders et al. U.S. Patent Publication # 2015/0071282 (hereinafter Anders) in view of Ammanur et al. U.S. Patent Publication # 2019/0132297 (hereinafter Ammanur)
With respect to claim 1, Anders teaches a communication chip, comprising:
-a first network processing die (Fig. 1 element 11) of a plurality of network processing dice (Fig. 1 element 11, 21, 31, 41, etc.), comprising a first external port (i.e. Fig. 4 NP out, 402 and SP out 406) and a first internal port (Fig. 4 element NP in 404, SP in 408)(Paragraph 58-59), and configured to:
-receive, from outside the communication chip and through the first external port, a first packet (i.e. router includes an input port to receive packet) (Paragraph 61);
-obtain destination information (i.e. destination address) that is of the first packet and that indicates a destination network processing die of the first packet (i.e. destination address may include address of a destination node for the packet)(Paragraph 54) and
-send, through the first internal port, a second packet comprising the destination information (Paragraph 98)
-a switching die (Fig. 1 element 100) configured to:
-receive, from the first network processing die, the second packet (Paragraph 98); and
-send, based on the destination information, the second packet (i.e. to route the second packet to second packet switched sideband data from the first router) (Paragraph 98-99, 102-103); and a second network processing die of the plurality of network processing dice, comprising a second external port (i.e. output port) (Paragraph 58-59) and a second internal port (i.e. another input port) (Paragraph 59), and configured to:
-receive, from the switching die, the second packet (Paragraph 98); and either: send, outside the communication chip and through the second external port, the second packet (Paragraph 98-99, 102-103); or send, to a third network processing die of the plurality of network processing dice and through the second internal port, the second packet.
Anders does not explicitly state a second packet comprising the first packet.
Ammanur teaches send, through the first internal port, a second packet comprising the first packet and the destination information (Paragraph 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Ammanur’s teaching in Anders’ teaching to come up with having second packet comprising the first packet and the destination information. The motivation for doing so would be to process and/or forward packets more quickly (Paragraph 36)
With respect to claim 2, Anders and Ammanur teaches the communication chip of claim 1, but Anders further teaches wherein the switching die is further configured to send, after receiving the second packet and to the second network processing die, path indication information indicating a sending path of the second packet (Paragraph 101, 107), and wherein the second network processing die is further configured to: receive the path indication information (i.e. route the packets using the destination address of the packet to determine a direction of a packet switched routing of the packet) (Paragraph 99, 107) ; and either: further send, based on the path indication information and through the second external port, the second packet (Paragraph 98-99, 102-103); or further send, to the third network processing die, through the second internal port, and based on the path indication information, the second packet.
With respect to claim 3, Anders and Ammanur teaches the communication chip of claim 2, but Anders further teaches wherein the second network processing die further comprises: a first selector switch comprising: a connection end connected to the switching die (Paragraph 36, 44); a first selection end connected to the second external port (Paragraph 58); and a second selection end connected to the second internal port (Paragraph 58-59), and wherein the second network processing die is further configured to: connect the connection end and the first selection end when sending the second packet outside the communication chip (Paragraph 60-63); and connect the connection end and the second selection end when sending the second to the third network processing die (Paragraph 60-63).
With respect to claim 5, Anders and Ammanur teaches the communication chip of claim 1, but Anders further teaches wherein the switching die is not connected to the destination network processing die, wherein at least two fourth network processing dice in in the plurality of network processing dice are connected to the switching die and the destination network processing die (Paragraph 68, 76), and wherein the switching die is further configured to further send, through one of the at least two fourth network processing dice, the second packet (Paragraph 103, 107)
With respect to claim 6, Anders and Ammanur teaches the communication chip of claim 1, but Anders further teaches wherein the first network processing die is not connected to the switching die, wherein after receiving the first packet, the first network processing die is further configured to further send, through the first internal port and to a fourth network processing die, the second packet, wherein the fourth network processing die is connected to the switching die, and wherein the fourth network processing die is configured to: receive the second packet (Paragraph 68, 76); and forward, to the switching die, the second packet (Paragraph 68, 76)
With respect to claim 7, Anders and Ammanur teaches the communication chip of claim 6, but Anders further teaches wherein the fourth network processing die comprises at least two fourth network processing dice in the plurality of network processing dice, and wherein the first network processing die is further configured to send, through one of the at least two fourth network processing dice, the second packet (Paragraph 68, 76)
With respect to claim 8, Anders and Ammanur teaches the communication chip of claim 7, but Anders further teaches wherein the first network processing die further comprises: a second selector switch comprising: a connection end connected to the first external port (Paragraph 68, 76); and at least two selection ends respectively connected to the at least two fourth network processing dice, and wherein the first network processing die is further configured to connect the connection end and one of the at least two selection ends to send the second packet (Paragraph 68, 76).
With respect to claim 9, Anders and Ammanur teaches the communication chip of claim 8, but Anders further teaches wherein the first network processing die is further configured to send, through the first external port, the first packet when the destination network processing die is the first network processing die (Paragraph 58, 61)
With respect to claim 11, Anders teaches apparatus, comprising: a backplane (Paragraph 57-60) and at least one communication chip disposed on the backplane (Paragraph 4, 6, 113) and comprising: a first network processing die of a plurality of network processing dice, comprising a first external port of a first internal port (Fig. 4 element NP in 404, SP in 408)(Paragraph 58-59), and configured to:
-receive, from outside the at least one communication chip and through the first external port, a first packet (i.e. router includes an input port to receive packet) (Paragraph 61);
-obtain destination information that is of the first packet and that indicates a destination network processing die of the first packet(i.e. destination address may include address of a destination node for the packet)(Paragraph 54); and
-send, through the first internal port, a second packet comprising the first packet and the destination information (Paragraph 98)
-a switching die configured to: receive, from the first network processing die, the second packet (Paragraph 98); and
-send, based on the destination information, the second packet (i.e. to route the second packet to second packet switched sideband data from the first router) (Paragraph 98-99, 102-103); and
-a second network processing die of the plurality of network processing dice, comprising a second external port (i.e. output port) (Paragraph 58-59) and a second internal port (i.e. another input port) (Paragraph 59) and configured to:
-receive, from the switching die, the second packet; and either: send, outside the at least one communication chip and through the second external port, the second packet; (Paragraph 98-99, 102-103); or send, to a third network processing die of the plurality of network processing dice and through the second internal port, the second packet.
Anders does not explicitly state a second packet comprising the first packet.
Ammanur teaches send, through the first internal port, a second packet comprising the first packet and the destination information (Paragraph 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Ammanur’s teaching in Anders’ teaching to come up with having second packet comprising the first packet and the destination information. The motivation for doing so would be to process and/or forward packets more quickly (Paragraph 36)
With respect to claim 13, Anders and Ammanur teaches the apparatus of claim 12, but Anders further teaches further comprising a switching box or a switching frame (Paragraph 26).
With respect to claim 14, Anders and Ammanur teaches the apparatus of claim 12, but Anders further teaches wherein when the apparatus comprises the switching frame, the switching frame comprises at least one line card corresponding to the at least one communication chip, and the at least one communication chip is disposed on the backplane via the at least one line card (Paragraph 6, 113)
With respect to claim 15, Anders teaches a switching device, comprising: a backplane (Paragraph 57-60) and at least one communication chip disposed on the backplane (Paragraph 4, 6, 113) and comprising: a first network processing die of a plurality of network processing dice, comprising a first external port of a first internal port (Fig. 4 element NP in 404, SP in 408)(Paragraph 58-59), and configured to:
-receive, from outside the at least one communication chip and through the first external port, a first packet (i.e. router includes an input port to receive packet) (Paragraph 61);
-obtain destination information that is of the first packet and that indicates a destination network processing die of the first packet(i.e. destination address may include address of a destination node for the packet)(Paragraph 54); and
-send, through the first internal port, a second packet comprising the first packet and the destination information (Paragraph 98)
-a switching die configured to: receive, from the first network processing die, the second packet (Paragraph 98); and
-send, based on the destination information, the second packet (i.e. to route the second packet to second packet switched sideband data from the first router) (Paragraph 98-99, 102-103); and
-a second network processing die of the plurality of network processing dice, comprising a second external port (i.e. output port) (Paragraph 58-59) and a second internal port (i.e. another input port) (Paragraph 59) and configured to:
-receive, from the switching die, the second packet; and either: send, outside the at least one communication chip and through the second external port, the second packet; (Paragraph 98-99, 102-103); or send, to a third network processing die of the plurality of network processing dice and through the second internal port, the second packet.
Anders does not explicitly state a second packet comprising the first packet.
Ammanur teaches send, through the first internal port, a second packet comprising the first packet and the destination information (Paragraph 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Ammanur’s teaching in Anders’ teaching to come up with having second packet comprising the first packet and the destination information. The motivation for doing so would be to process and/or forward packets more quickly (Paragraph 36)
With respect to claim 16-17, 19-20, respectively, teaches same limitations as claims 2-3, 5-6 respectively, therefore rejected under same basis.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anders et al. U.S. Patent Publication # 2015/0071282 (hereinafter Anders) in view of Ammanur et al. U.S. Patent Publication # 2019/0132297 (hereinafter Ammanur) further in view of Chen et al. U.S. Patent Publication # 2016/0240497 (hereinafter Chen)
With respect to claim 10, Anders and Ammanur teaches the communication chip of claim 1, but does not explicitly show wherein the switching die and the plurality of network processing dice are located in a same wafer.
Chen teaches wherein the switching die and the plurality of network processing dice are located in a same wafer (Paragraph 80). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Chen’s teaching in Anders and Ammanur’s teaching to come up with having plurality of dice are located in a same wafer. The motivation for doing so would be simply the switch fabric of the packet switching circuit.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anders et al. U.S. Patent Publication # 2015/0071282 (hereinafter Anders) in view of Ammanur et al. U.S. Patent Publication # 2019/0132297 (hereinafter Ammanur) further in view of Branco et al. U.S. Patent Publication # 2020/0264988 (hereinafter Branco)
With respect to claim 11, Anders and Ammanur teaches the communication chip of claim 1, but does not explicitly teaches wherein the communication chip further comprises a plurality of storage dice, and wherein the first network processing die is connected to one or more of the plurality of storage dice.
Branco teaches wherein the communication chip further comprises a plurality of storage dice, and wherein the first network processing die is connected to one or more of the plurality of storage dice (Paragraph 12). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Branco’s teaching in Anders and Ammanur’s teaching to come up with having plurality of storage device connected with network processing die. The motivation for doing so would be to compile a program using system memory thereby limiting general security vulnerabilities.
Allowable Subject Matter
Claims 4, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A). Lu et al. 2017/0118140 which teaches about network switch having identical dies and interconnection network packaged in the same package.
B). Lambert et al. U.S. Patent Publication # 2014/0250239 which teaches about creating a second packet by using the deconstructed first packet.
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DHAIRYA A. PATEL
Primary Examiner
Art Unit 2453
/DHAIRYA A PATEL/Primary Examiner, Art Unit 2453
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