CTNF 18/929,218 CTNF 99317 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority This application claims benefit of foreign priority under 35 U.S.C. 119(a)-(d) of Application No. CN202210473780.6 and CN202210934646.1 , filed in China on 04/29/2022 and 08/04/2022 . Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/08/2025 and 08/08/2025 was considered by the examiner. 07-30-03-h AIA Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Claims 9-10 and 12 recite the limitation “ communication interface . These limitations have been interpreted under 112(f) as a means plus function because of the combination of the non-structural, generic placeholder “ communication interface and is being interpreted as “ communication interface 1001 ” that corresponds to the structure found in the disclosure (Par. [0140] and [0135] and Figs. 9-10). Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. “Chip” and “circuit” of Claim 9 are understood to be hardware elements having their usual technical meanings and are not understood to be nonce words. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (U.S. Patent App. Pub No. 2022/0398685 A1, hereafter referred as Jeon) in view of Sindhu et al. (U.S. Patent App. Pub No. 2019/0012278 A1, hereafter referred as Sindhu) . Regarding Claim 1 : Jeon teaches a method, the method comprising: obtaining, by the DPU, image data comprised of a plurality of encoded images (Jeon: Par. [0065]; Referring to FIG. 1A, an image may be fetched from a storage of the AI server in a form of a JPEG file, as a non-limiting example, by a loader 111 in operation 103. A label of the image may be transmitted or provided, e.g., by the loader 111, to the GPU for the AI training. Preprocessing of data for the training of an AI model by the AI server, for example, may be performed by the storage device 101 in operation 104 of FIG. 1A.) ; performing, by the DPU, at least one operation in an image processing operation set on the image data to obtain model training data, wherein at least one operation of processing the image data comprises the at least one operation in the image processing operation set and at least one second operation of processing the image data comprises an operation in a training operation set, the image processing operation set comprises at least one image decoding operation, and the training operation set comprises at least one model training operation (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) ; and outputting, by the DPU, the model training data, wherein the model training data is useable by the model training processor to perform the operation in the training operation set, or the model training data is useable by the CPU and a model training processor to perform the operation in the training operation set (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) . Jeon fails to teach wherein a data processing unit (DPU) is separately coupled to a central processing unit (CPU) and a model training processor through a system bus, or the DPU and the model training processor are different chips on one training card. Sindhu, like Jeon, is directed to data processing. Sindhu does teach wherein a data processing unit (DPU) is separately coupled to a central processing unit (CPU) and a model training processor through a system bus, or the DPU and the model training processor are different chips on one training card (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon to utilize the separate processing units, as taught by Sindhu, to arrive at the claimed invention discussed above. Such a modification is the result of combining prior art elements according to known methods to yield predictable results. As taught by Sindhu, the proposed modification would reduce its processing load, such that the application processor can perform those computing tasks for which the application processor is well suited, and offload data-focused tasks for which the application processor may not be well suited (Sindhu: Par. [0007]) . In regards to Claim 2 , Jeon as modified by Sindhu further teaches the method according to claim 1, wherein the DPU comprises a network interface, and obtaining, by the DPU, the image data comprises: obtaining, by the DPU, the image data via a wired network or a wireless network (Sindhu: Par. [0008]; The DPU may support one or more high-speed network interfaces, such as Ethernet ports, without the need for a separate network interface card (NIC), and may include programmable hardware specialized for network traffic) . In regards to Claim 3 , Jeon as modified by Sindhu further teaches the method according to claim 2, wherein the wired network is an Ethernet or a wireless bandwidth network (Sindhu: Par. [0008]; The DPU may support one or more high-speed network interfaces, such as Ethernet ports, without the need for a separate network interface card (NIC), and may include programmable hardware specialized for network traffic) . In regards to Claim 4 , Jeon as modified by Sindhu further teaches the method according to claim 1, wherein the DPU is connected to a storage device, and obtaining, by the DPU, the image data comprises: obtaining, by the DPU, the image data from the storage device (Jeon: Par. [0085]; When the decoded data is not present or available in the second memory 136, the processor 120 may fetch the raw data stored in the first memory 133, decode the data by the decoder 170, and augment the decoded data through the idle augmentation module among the target augmentation modules. The decoded data may be stored in the second memory 136, e.g., so that a decoding process may not be repeatedly performed when the same raw data is subsequently input) . In regards to Claim 5 , Jeon as modified by Sindhu further teaches the method according to claim 1 wherein the image processing operation set further comprises at least one image data transformation operation, and performing, by the DPU, the at least one operation in the image processing operation set on the image data to obtain the model training data comprises: performing, by the DPU, the at least one image decoding operation on the image data to obtain matrix data; and performing, by the DPU, the at least one image data transformation operation on the matrix data to obtain the model training data (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) . In regards to Claim 6 , Jeon as modified by Sindhu further teaches the method according to claim 1, wherein the training operation set further comprises at least one image data transformation operation, the model training data is used by the CPU to perform the at least one image data transformation operation to obtain temporary data, and the temporary data is used by the model training processor to perform the at least one model training operation (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) . In regards to Claim 7 , Jeon as modified by Sindhu further teaches the method according to claim 1, further comprising: obtaining, by the DPU, an artificial intelligence (AI) model output from the model training processor; and sending, by the DPU, the AI model to a local storage device or a remote storage device, wherein the AI model is stored in the local storage device or the remote storage device in a file format or a key-value (KV) format (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) . In regards to Claim 8 , Jeon as modified by Sindhu further teaches the method according to claim 1, wherein outputting, by the DPU, the model training data comprises: outputting, by the DPU, the model training data to a second DPU, wherein the second DPU is separately coupled to a second CPU and a second model training processor through a system bus, or the second DPU and the second model training processor are different chips on one training card, and the second DPU is configured to (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) : receive the model training data, and output the model training data to the second model training processor, wherein the model training data is used by the second model training processor to perform the operation in the training operation set (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) . Regarding Claim 9 : Jeon as modified by Sindhu further teaches a first data processing unit (DPU), comprising: a communication interface, configured to obtain image data comprised of a plurality of encoded images (Jeon: Par. [0065]; Referring to FIG. 1A, an image may be fetched from a storage of the AI server in a form of a JPEG file, as a non-limiting example, by a loader 111 in operation 103. A label of the image may be transmitted or provided, e.g., by the loader 111, to the GPU for the AI training. Preprocessing of data for the training of an AI model by the AI server, for example, may be performed by the storage device 101 in operation 104 of FIG. 1A.) ; a processing chip, configured to perform at least one operation in an image processing operation set on the image data to obtain model training data, wherein at least one operation of processing the image data comprises the at least one operation in the image processing operation set and at least one second operation of processing the image data comprises an operation in a training operation set, the image processing operation set comprises at least one image decoding operation, and the training operation set comprises at least one model training operation (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) ; and an output interface circuit, configured to output the model training data, wherein the model training data is useable by a first model training processor to perform the operation in the training operation set, or the model training data is useable by a first central processing unit (CPU) and a first model training processor to perform the operation in the training operation set (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) , wherein the first DPU is separately coupled to the first CPU and the first model training processor through a system bus, or the first DPU and the first model training processor are different chips on one training card (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . In regards to Claim 10 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the image processing operation set further comprises at least one image data transformation operation, and the processing chip is configured to: perform the at least one image decoding operation on the image data to obtain matrix data; and perform the at least one image data transformation operation on the matrix data to obtain the model training data (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) . In regards to Claim 11 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the training operation set further comprises at least one image data transformation operation, the model training data is used by the first CPU to perform the at least one image data transformation operation to obtain temporary data, and the temporary data is used by the first model training processor to perform the at least one model training operation (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) . In regards to Claim 12 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the communication interface is configured to: obtain an artificial intelligence (AI) model output from the first model training processor; and send the AI model to a local storage device or a remote storage device, wherein the AI model is stored in the local storage device or the remote storage device in a file format or a key-value (KV) format (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) . In regards to Claim 13 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the output interface circuit is further configured to output the model training data to a second DPU; and the second DPU is separately coupled to a second CPU and a second model training processor through a system bus, or the second DPU and the second model training processor are different chips on one training card, and the second DPU is configured to (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) : receive the model training data; and output the model training data to the second model training processor, wherein the model training data is used by the second model training processor to perform the operation in the training operation set (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) . In regards to Claim 14 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the communication interface is an Ethernet or a wireless bandwidth network (Sindhu: Par. [0008]; The DPU may support one or more high-speed network interfaces, such as Ethernet ports, without the need for a separate network interface card (NIC), and may include programmable hardware specialized for network traffic) . In regards to Claim 15 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the first DPU is connected to a storage device, the storage device comprising: one or more of a hard disk drive (HDD), a flash media drive, shingled magnetic recording (SMR), a storage array, or a storage server (Jeon: Par. [0077]; In one example, the storage device 101 may include a first memory 133 configured to store therein raw data to be preprocessed, and an SSD controller 135 configured to control reading and writing of data from and in the first memory 133. The first memory 133 may be a flash memory, as a non-limiting example.) . In regards to Claim 16 , Jeon as modified by Sindhu further teaches the first DPU according to claim 15, wherein a communication protocol between the storage device and the first DPU comprises one or more of a small computer system interface (SCSI) protocol, a serial attached small computer system interface (SAS) protocol, a peripheral component interconnect express (PCIe) protocol, a universal serial bus (USB) protocol, or a non-volatile memory express (NVMe) protocol (Sindhu: Par. [0007] and [0062]; Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . In regards to Claim 17 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the DPU, the CPU, and the first model training processor are located on a same server (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . In regards to Claim 18 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the first model training processor is one or more of a graphics processing unit (GPU), a neural network processing unit (NPU), or a tensor processing unit (TPU) (Sindhu: Par. [0007] and [0062]; Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . In regards to Claim 19 , Jeon as modified by Sindhu further teaches the first DPU according to claim 9, wherein the system bus comprises one or more of a peripheral component interconnect express (PCIe) bus, a compute express link (CXL) bus, or a non-volatile memory express (NVMe) bus (Sindhu: Par. [0007] and [0062]; Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . Regarding Claim 20 : Jeon as modified by Sindhu further teaches a data processing unit (DPU), comprising: a communication interface, configured to obtain image data comprised of a plurality of encoded images (Jeon: Par. [0065]; Referring to FIG. 1A, an image may be fetched from a storage of the AI server in a form of a JPEG file, as a non-limiting example, by a loader 111 in operation 103. A label of the image may be transmitted or provided, e.g., by the loader 111, to the GPU for the AI training. Preprocessing of data for the training of an AI model by the AI server, for example, may be performed by the storage device 101 in operation 104 of FIG. 1A.) ; a processing chip, configured to perform at least one operation in an image processing operation set on the image data to obtain model training data, wherein at least one operation of processing the image data comprises the at least one operation in the image processing operation set and at least one second operation of processing the image data comprises an operation in a training operation set, the image processing operation set comprises at least one image decoding operation, and the training operation set comprises at least one model training operation (Jeon: Par. [0066]; the preprocessing operation 104 may include decoding by a decoder 105, resizing by a resizer 107, and augmentation by augmenter 109, e.g., where the illustrated decoder 105, resizer 107, and augmenter 109 are components or other hardware modules implemented by the storage device 101. The augmentation may be a process of increasing data to improve the accuracy for the AI training by the AI server 100. Examples of various augmentation methods will be described further below with reference to FIG. 1B, as non-limiting examples.) ; and a data read/write interface, configured to write the model training data into a shared cache that is accessed by a plurality of model training processors, wherein the model training data in the shared cache is used by the plurality of model training processors to perform the operation in the training operation set, or the model training data in the shared cache is used by a central processing unit (CPU) and the plurality of model training processors to perform the operation in the training operation set (Jeon: Par. [0118]; In operation 650, the processor 120 may transmit or provide the augmented data to the GPU 190. As described above with reference to FIG. 2, the augmented data may be transmitted or provided to the GPU 190 without passing through a CPU 180, and thus the usage of CPU resources may be improved; Par. [0010]; the GPU may be configured to train an AI model using the augmented data as training data) , wherein the DPU is separately coupled to the CPU and the plurality of model training processors through a system bus, or the DPU and the plurality of model training processors are different chips on one training card (Sindhu: Par. [0007] and [0062]; In some cases, an application processor (e.g., a separate processing device, server, storage device or even a local CPU and/or local graphics processing unit (GPU) of the compute node hosting the DPU) may programmatically interface with the DPU to configure the DPU as needed and to offload any data-processing intense tasks; DPU 130 generally represents a hardware chip implemented in digital logic circuitry. DPU 130 may operate substantially similar to any of the DPUs of the devices within racks 20, 22, 24, or 26 of FIG. 1A, DPU 102A of FIG. 1B, DPU 102B of FIG. 1C, or DPU 102C of FIG. 1D. Thus, DPU 130 may be communicatively coupled to a CPU, a GPU, one or more network devices, server devices, random access memory, storage media (e.g., solid state drives (SSDs)), a data center fabric, or the like, e.g., via PCI-e, Ethernet (wired or wireless), or other such communication media) . Pertinent Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gold et al. (U.S. Patent App. Pub No. 2019/0121566 A1) teaches data transformation offloading in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RENAE BITOR whose telephone number is (703)756-5563. The examiner can normally be reached Monday to Friday: 8:00 - 5:30 but off the 1st Friday of the biweek. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RENAE A BITOR/Examiner, Art Unit 2663 /GREGORY A MORSE/Supervisory Patent Examiner, Art Unit 2698 Application/Control Number: 18/929,218 Page 2 Art Unit: 2663 Application/Control Number: 18/929,218 Page 3 Art Unit: 2663 Application/Control Number: 18/929,218 Page 4 Art Unit: 2663 Application/Control Number: 18/929,218 Page 5 Art Unit: 2663 Application/Control Number: 18/929,218 Page 6 Art Unit: 2663 Application/Control Number: 18/929,218 Page 7 Art Unit: 2663 Application/Control Number: 18/929,218 Page 8 Art Unit: 2663 Application/Control Number: 18/929,218 Page 9 Art Unit: 2663 Application/Control Number: 18/929,218 Page 10 Art Unit: 2663 Application/Control Number: 18/929,218 Page 11 Art Unit: 2663 Application/Control Number: 18/929,218 Page 12 Art Unit: 2663 Application/Control Number: 18/929,218 Page 13 Art Unit: 2663 Application/Control Number: 18/929,218 Page 14 Art Unit: 2663 Application/Control Number: 18/929,218 Page 15 Art Unit: 2663 Application/Control Number: 18/929,218 Page 16 Art Unit: 2663 Application/Control Number: 18/929,218 Page 17 Art Unit: 2663 Application/Control Number: 18/929,218 Page 18 Art Unit: 2663 Application/Control Number: 18/929,218 Page 19 Art Unit: 2663
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