DETAILED ACTION
Claims 1-20 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/04/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 12-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bernasconi et al. (US-20090201049), hereinafter Bernasconi.
Claim 1:
Bernasconi teaches a device (Fig. 4, Bolton pad P) comprising:
a shared pad (Fig. 4, PB);
a first buffer (Fig. 4, QB) including an input coupled to the shared pad (Fig. 4, PB), wherein the first buffer includes an output;
a first boundary cell (Fig. 4, BC1) coupled to the output of the first buffer (Fig. 4, QB);
a circuit (Fig. 4, PLM);
a first logic gate (Fig. 4, OR2) including an input coupled to the circuit; and
a second boundary cell (Fig. 4, BC2) coupled to the first buffer (Fig. 4, QB) and coupled to the first logic gate (Fig. 4, OR2).
Claim 2:
Bernasconi teaches the first buffer (Fig. 4, QB) includes an enable terminal (Fig. 4, output from OR2) coupled to the second boundary cell (Fig. 4, BC2).
Claim 3:
Bernasconi teaches the first logic gate (Fig. 4, OR2) is an inverter gate including an output coupled to the second boundary cell.
Claim 4:
Bernasconi teaches an analog data path (Fig. 4, IB1 and IB2) coupled to the shared pad (Fig. 4, PB).
Claim 5:
Bernasconi teaches a multiplexer (Fig. 4, M3) coupled to the second boundary cell and coupled to the first buffer.
Claim 6:
Bernasconi teaches a core data register (Fig. 4, provide signal gpio_oen) coupled to the multiplexer (Fig. 4, M3), wherein the multiplexer (Fig. 4, M3) includes an output, and wherein the first buffer (Fig. 4, QB) includes an enable terminal (Fig. 4, output from OR2) coupled to the output of the multiplexer.
Claim 7:
Bernasconi teaches a second logic gate (Fig. 4, OR1) including: a first input coupled to the circuit; and an output, wherein the first buffer includes a pull input coupled to the output of the second logic gate.
Claim 8:
Bernasconi teaches the second logic gate (Fig. 4, OR1) is an OR gate including a second input coupled to the input of the first logic gate.
Claim 12:
Bernasconi teaches a device (Fig. 4, Bolton pad P) comprising:
an analog domain (Fig. 4, IB1 and IB2);
a shared pad (Fig. 4, PB) coupled to the analog domain; and
a digital domain (Fig. 4, PLM) coupled to the shared pad (Fig. 4, PB), wherein the digital domain includes:
a first buffer (Fig. 4, QB) including a first input coupled to the shared pad,
wherein the first buffer includes an enable input (Fig. 4, output from OR2);
a circuit (Fig. 4, PLM); and
a first boundary cell (Fig. 4, BC1) coupled to the circuit (Fig. 4, PLM) and coupled to the enable input of the first buffer (Fig. 4, QB).
Claim 13:
Bernasconi teaches an analog pad (Fig. 4, IB1 and IB2) separate from the shared pad and coupled to the analog domain.
Claim 14:
Bernasconi teaches a multiplexer (Fig. 4, M3) including: a first input coupled to the first boundary cell (Fig. 4, BC1); and an output coupled to the enable input (Fig. 4, output from OR2) of the first buffer (Fig. 4, QB).
Claim 15:
Bernasconi teaches a core data register (Fig. 4, provide signal gpio_oen), wherein the multiplexer includes a second input coupled to the core data register.
Claim 16:
Bernasconi teaches the first buffer (Fig. 4, QB) includes a pull input, the device further comprising a logic gate (Fig. 4, OR2) including: a first input coupled to the circuit; and an output coupled to the pull input of the first buffer (Fig. 4, QB).
Claim 17:
Bernasconi teaches a logic gate (Fig. 4, OR2) including: an input coupled to the circuit; and an output coupled to the first boundary cell.
Claim 18:
Bernasconi teaches a device (Fig. 4, Bolton pad P) comprising:
an analog domain (Fig. 4, IB1 and IB2);
a shared pad (Fig. 4, PB) coupled to the analog domain; and
a digital domain (Fig. 4, PLM) coupled to the shared pad, wherein the digital domain includes:
a first buffer (Fig. 4, QB) including a first input coupled to the shared pad (Fig. 4, PB, wherein the first buffer includes an enable input (Fig. 4, output from OR2), a pull input, and an output;
a circuit (Fig. 4, PLM);
a first logic gate (Fig. 4, OR2) coupled to the circuit and coupled to the pull input of the first buffer;
a first boundary cell (Fig. 4, BC1) coupled to the circuit (Fig. 4, PLM) and the enable input of the first buffer (Fig. 4, output from OR2);
a second boundary cell (Fig. 4, BC2) coupled to the circuit (Fig. 4, PLM); and
a second buffer (Fig. 4, IB2) including:
a first input (Fig. 4, output IB1);
an enable input (Fig. 4, output tcb_p1) coupled to the second boundary cell; and
an output coupled to the shared pad (Fig. 4, PB).
Claim 20:
Bernasconi teaches a core data register (Fig. 4, provide signal gpio_oen); and a multiplexer (Fig. 4, M3) including: a first input coupled to the first boundary cell; a second input coupled to the core data register; and an output coupled to the enable input of the first buffer.
Allowable Subject Matter
Claims 9-11 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US-20120216089) teaches the integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit. (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 02/07/2026
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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