DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 04/13/2026. Claims 1-16 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/13/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference Cao US 2024/0385978 is cited in this Office Action.
In view of the new reference, independent claims 1 and 9 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty US 2020/0012451 (“Benisty”) in view of Choi et al. US 2015/0143035 (“Choi”) and in further view of Cao 2024/0385978 (“Cao”).
As per independent claim 1, Benisty teaches A command information distribution method for a rewritable non-volatile memory module (“A method and apparatus for operating a solid state drive is disclosed” para 0008), the command information distribution method comprising:
arranging a plurality of first command queues used to cache in parallel command information (“The host computer system 300 has a host memory that has submission queues 308,” Para 0059 and FIG. 3. “In order to increase the performance of the solid state drive, the device may execute several commands in parallel.” Para 0067);
arranging a plurality of second command queues used to cache in parallel command information to be transmitted to the rewritable non-volatile memory module (“The commands are arbitrated according to a selected scheme, and then sent to command queueing 332 through the PCIe MAC PHY interconnection 326. Several queues may be used or filled when the command queueing arrangement 332 performs arbiter activities.” Para 0062 and FIG. 3. “In order to increase the performance of the solid state drive, the device may execute several commands in parallel.” Para 0067);
extracting first command information from a first target queue among the plurality of first command queues according to weight information corresponding to the plurality of first command queues (“the memory device may use an arbitration algorithm, such as a round-robin algorithm or a weighted round-robin algorithm. These algorithms may determine the order in which to fetch commands from multiple submission queues as well as administrative queues.” Para 0036 and FIGS. 1 and 2);
performing information format processing on the first command information to generate second command information (“When commands are received from the submission queues 308 … a doorbell time stamp may be attached by a doorbell time stamp arrangement 336 to aid in the command arbitration 330 ….” Para 0062 and FIG. 3);
distributing the second command information to a second target queue among the plurality of second command queues to wait for execution by the rewritable non-volatile memory module (“The commands are arbitrated according to a selected scheme, and then sent to command queueing 332 through the PCIe MAC PHY interconnection 326. Several queues may be used or filled when the command queueing arrangement 332 performs arbiter activities.” Para 0062 and FIG. 3).
Benisty discloses all of the claim limitations from above, but does not explicitly teach “from a flash translation layer” and “wherein an information format of the first command information does not comply with a command information format supported by the rewritable non-volatile memory module while an information format of the second command information complies with the command information format supported by the rewritable non-volatile memory module”.
However, in an analogous art in the same field of endeavor, Choi teaches from a flash translation layer (“The user device 2000 … manages a FTL [Flash Translation Layer] on the host 2100, and if a specific condition is satisfied, the user device 2000 sends a read hint command to the storage device 2200 prior to a transfer of a read command.” Para 0136 and FIG. 2. See CMD queue 2131 in FIG. 2).
Given the teaching of Choi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty with “from a flash translation layer”. The motivation would be that a storage device may improve program/read performance using page offset in a read hint command from a host, para 0136 of Choi.
Benisty in combination with Choi discloses all of the claim limitations from above. Additionally, Choi teaches “The command manager 2234 is a module that analyzes a command received from the host 2100 and converts the command to be suitable for transmission to the flash memory 2210.” Paragraph [0063]. Nevertheless, for explicit teaching of a command supported by a non-volatile memory device, the new reference Cao is being relied upon herein.
Cao teaches wherein an information format of the first command information does not comply with a command information format supported by the rewritable non-volatile memory module while an information format of the second command information complies with the command information format supported by the rewritable non-volatile memory module (“the I/O request may be generated by an application running on the processor. … the I/O request may be converted by a device driver running on the processor into one or more request commands in a format supported by the memory device.” Para 0011. “the memory device may include a Universal Flash Memory (UFS) device.” Para 0013).
Given the teaching of Cao, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty and Choi with “wherein an information format of the first command information does not comply with a command information format supported by the rewritable non-volatile memory module while an information format of the second command information complies with the command information format supported by the rewritable non-volatile memory module”. The motivation would be that by converting the command, the command would be compatible with the UFS device, para 0013 of Cao.
As per dependent claim 2, Benisty in combination with Choi and Cao discloses the method of claim 1. Benisty teaches further comprising: setting a weight value corresponding to each of the plurality of first command queues according to the number of command information cached in each of the plurality of first command queues (“Referring to FIG. 2, an NVMe [Non Volatile Memory Express] Weighted Round Robin (WRR) arbiter is illustrated. … commands are broken into urgent, high priority, medium priority, low priority and an ASQ section. ASQ's proceed under strict priority 1, …. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority.” Para 0050 and FIG. 2).
As per dependent claim 3, Benisty in combination with Choi and Cao discloses the method of claim 1. Benisty teaches wherein the step of extracting the first command information from the first target queue among the plurality of first command queues according to the weight information corresponding to each of the plurality of first command queues comprises: in a queue selection operation, comparing weight values corresponding to each of the plurality of first command queues; and selecting one of the plurality of first command queues as the first target queue according to a comparison result (“Referring to FIG. 2, an NVMe Weighted Round Robin (WRR) arbiter is illustrated. … commands are broken into urgent, high priority, medium priority, low priority and an ASQ section. ASQ's proceed under strict priority 1, the highest priority possible. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority. Etc.” Para 0050 and FIG. 2).
As per claims 9-11, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-3. “A method and apparatus for operating a solid state drive is disclosed” para 0008 of Benisty.
Claims 4, 8, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Cao and in further view of Zhu et al. US 2021/0019085 (“Zhu”).
As per dependent claim 4, Benisty in combination with Choi and Cao discloses the method of claim 3. Benisty, Choi, and Cao may not explicitly disclose, but in an analogous art in the same field of endeavor, Zhu teaches further comprising: in response to a first candidate queue among the plurality of first command queues being selected as the first target queue for multiple consecutive times, updating a count value corresponding to the first candidate queue; and in response to the count value satisfying a predetermined condition, marking the first candidate queue so that the first candidate queue is excluded in the next queue selection operation (“At operation 720, the processing logic determines a difference value between the quota of commands and a count of commands previously selected from the respective queue … At operation 730, the processing logic determines … by excluding any queue … having a negative number for the respective difference value ….” Para 0098 and FIG. 7).
Given the teaching of Zhu, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty, Choi, and Cao with “further comprising: in response to a first candidate queue among the plurality of first command queues being selected as the first target queue for multiple consecutive times, updating a count value corresponding to the first candidate queue; and in response to the count value satisfying a predetermined condition, marking the first candidate queue so that the first candidate queue is excluded in the next queue selection operation”. The motivation would be that a worst case latency can be improved using quota, para 0015 of Zhu.
As per dependent claim 8, Benisty in combination with Choi and Cao discloses the method of claim 1. Benisty teaches wherein the rewritable non-volatile memory module comprises a plurality of memory chips (“multiple two dimensional memory arrays or three dimensional memory arrays may be formed on separate chips and then packaged together to form a stacked-chip memory device.” Para 0080).
Benisty, Choi, and Cao may not explicitly disclose, but in an analogous art in the same field of endeavor, Zhu teaches and the first target queue and the second target queue correspond to the same memory chip among the plurality of memory chips (“The controller 115 manages a number of queues 202-208 within the controller 115” para 0027 and FIG. 2).
Given the teaching of Zhu, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty, Choi, and Cao with “and the first target queue and the second target queue correspond to the same memory chip among the plurality of memory chips”. The motivation would be that the command queues can improve request traffic throughput, para 0024 of Zhu.
As per dependent claims 12 and 16, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 4 and 8.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Cao and in further view of Zhu and in further view of Matveyenko et al. US 2022/0253249 (“Matveyenko”).
As per dependent claim 5, Benisty in combination with Choi, Cao, and Zhu discloses the method of claim 4. Benisty, Choi, Cao, and Zhu may not explicitly disclose, but in an analogous art in the same field of endeavor, Matveyenko teaches further comprising: in response to the first candidate queue not being selected as the first target queue for consecutive times, resetting the count value corresponding to the first candidate queue (“the command could be considered starved when the age counter reaches zero” para 0038).
Given the teaching of Matveyenko, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty, Choi, Cao, and Zhu with “further comprising: in response to the first candidate queue not being selected as the first target queue for consecutive times, resetting the count value corresponding to the first candidate queue”. The motivation would be that age tracking can improve QoS, para 0021 of Matveyenko.
As per dependent claim 13, this claim is rejected based on arguments provided above for similar rejected dependent claim 5.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Cao and in further view of Donley et al. US 2022/0100411 (“Donley”).
As per dependent claim 6, Benisty in combination with Choi and Cao discloses the method of claim 1. Benisty teaches in response to the first target command information and at least one third target command information in the first target queue satisfying a second condition, adjusting the at least one third target command information to be sequenced after the first target command information (“ASQ's proceed under strict priority 1, the highest priority possible. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority.” Para 0050 and FIG. 2);
Benisty, Choi, and Cao may not explicitly disclose, but in an analogous art in the same field of endeavor, Donley teaches further comprising: performing command merging on the first target queue (“identifying (402) … from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination” para 0053 and FIGS. 4-5);
in the command merging, selecting first target command information in the first target queue and traversing remaining command information in the first target queue based on the first target command information; in response to the first target command information and at least one second target command information in the first target queue satisfying a first condition, merging the first target command information and the at least one second target command information (“determining (404) … in dependence upon a set of conditions, whether two or more candidate write transactions are combinable, combining (406) … the at least two candidate write transactions into a combined write transaction,” para 0053 and FIGS. 4-5);
ending the command merging after detecting last command information (“determining (404) … in dependence upon a set of conditions, whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5. All transactions in the queue are considered) or command information with a barrier flag in the first target queue.
Given the teaching of Donley, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty, Choi, and Cao with “further comprising: performing command merging on the first target queue” and “in the command merging, selecting first target command information in the first target queue and traversing remaining command information in the first target queue based on the first target command information; in response to the first target command information and at least one second target command information in the first target queue satisfying a first condition, merging the first target command information and the at least one second target command information” and “ending the command merging after detecting last command information or command information with a barrier flag in the first target queue”. The motivation would be that the command queues can improve request traffic throughput, para 0024 of Zhu.
As per dependent claim 7, Benisty in combination with Choi, Cao, and Donley discloses the method of claim 6. Benisty, Choi, and Cao may not explicitly disclose, but Donley teaches further comprising: in response to the first target command information and the at least one second target command information belonging to a same type of commands (“determining (404) … whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5) and the first target command information and the at least one second target command information corresponding to a same memory page or different memory planes, determining that the first target command information and the at least one second target command information satisfy the first condition (“two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction also includes determining (504) whether an offset entry of the incoming write transaction and an offset entry of the existing write transaction are consecutive.” Para 0055);
in response to the first target command information and the at least one third target command information belonging to the same type of commands (“determining (404) … whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5) and the first target command information and the at least one third target command information corresponding to a plurality of consecutive memory pages, determining that the first target command information and the at least one third target command information satisfy the second condition (“two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction also includes determining (504) whether an offset entry of the incoming write transaction and an offset entry of the existing write transaction are consecutive.” Para 0055).
The same motivation that was utilized for combining Benisty and Donley as set forth in claim 6 is equally applicable to claim 7.
As per dependent claims 14-15, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 6-7.
Conclusion
Another reference Perry et al. US 2022/0365688 (“Perry”) was considered by the Examiner. Perry teaches “The controller may expose the memory block device to the computing device as a Non-Volatile Memory Express (“NVMe”) target device, and may control access to the memory block device by converting NVMe access requests in a first format from the computing device to access requests in a different second format supported by the memory block device.” Abstract of Perry. Therefore, Perry negates the patentability of the instant claimed invention.
Another reference Chan US 2018/0018132 (“Chan”) was considered.
Chan teaches “According to FIG. 2, when CSb signal 200 supplied to the CSb pin is driven from a high level to a low level, serial input (SI) signal 210 including an instruction sequence 250 is supplied to the SI pin of memory device 100, Instruction sequence 250 includes a program instruction 252, an address 254, and a series of input data units 258 to be programmed into memory array 110. Program instruction 252, address 254, and the series of input data units 258 are serially transmitted from the external device. In the embodiment illustrated in FIG. 2, program instruction 252 is an 8-bit instruction code “02h”, which instructs memory device 100 to execute a program operation. Address 254 consists of 24 bits of address data, and represents an initial address n of a location in memory array 110 into which the plurality of input data units 280 are to be programmed.” Paragraph [0024]. This description by Chan is similar to the description found in paragraph [0060] of the instant filed specification which was cited as support for the amendment. Therefore, Chan appears to negate the patentability of the instant claimed invention.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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