DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 12/22/2025. Claims 1-16 have been examined and are pending in this application.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
Applicant argues, page 10 of the remarks, “[as] is well known, the FTL resides inside the flash controller and performs LBA-to-PBA translation (see Background, paragraph [0003] of the as-filed application).
The Examiner respectfully submits that an FTL [Flash Translation Layer] can reside in a flash controller as well as in a host memory for the purposes of address translation. Applicant’s filed specification at paragraph [0003] does not necessarily describe that an FTL resides in a flash controller. Nevertheless, it is known that an FTL can reside in the memory of a flash controller. By the same token, an FTL can also reside in the memory of a host. For example, the secondary reference Choi describes a host FTL (see FIG. 2 of Choi) residing in a buffer RAM 2140 (emphasis added) in the host. As cited before in the previous Office Action, Choi teaches “The user device 2000 … manages a FTL on the host 2100,” paragraph [0136] of Choi.
Applicant argues, page 11 of the remarks, “if the Examiner equates Benisty’s ‘submission queue 308’ with Claim 1’s ‘plurality of first command queues (see OA’s pages 2-3)’, then the submission queue 308 should be located inside Benisty’s device controller 324, specifically between the FTL and the memory array.”
The Examiner respectfully disagrees. Applicant’s above argument is based on the fatal assumption that an FTL is always located in the memory of a flash controller. Benisty does not describe that its FTL is located in the memory of a flash controller. The claimed invention also does not require that the FTL be located in the memory of a flash controller (emphasis added). The secondary reference Choi teaches that the FTL is located in a buffer RAM 2140 of the host.
Applicant argues, page 11 of the remarks, “[however], as shown in FIG. 3 of Benisty, the submission queue 308 is located in the host memory of computer system 300, rather than inside device controller 324, and certainly not between the FTL and the memory array. In other words, the submission queue 308 buffers commands headed to the FTL, not commands coming from the FTL.”
The Examiner respectfully disagrees. Once again, Applicant’s above argument is based on the fatal assumption that an FTL is always located in the memory of a flash controller. Benisty (the primary reference) teaches that the submission queue 308 is located inside a host memory. Choi (the secondary reference) teaches that the FTL is located in a buffer RAM of the host. Most importantly, the claim does not require that the FTL is located in the memory of a flash controller (emphasis added). Therefore, the combination teaches commands coming from the FTL.
In view of the foregoing remarks, independent claims 1 and 9 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty US 2020/0012451 (“Benisty”) in view of Choi et al. US 2015/0143035 (“Choi”).
As per independent claim 1, Benisty teaches A command information distribution method for a rewritable non-volatile memory module (“A method and apparatus for operating a solid state drive is disclosed” para 0008), the command information distribution method comprising:
arranging a plurality of first command queues used to cache in parallel command information (“The host computer system 300 has a host memory that has submission queues 308,” Para 0059 and FIG. 3. “In order to increase the performance of the solid state drive, the device may execute several commands in parallel.” Para 0067);
arranging a plurality of second command queues used to cache in parallel command information to be transmitted to the rewritable non-volatile memory module (“The commands are arbitrated according to a selected scheme, and then sent to command queueing 332 through the PCIe MAC PHY interconnection 326. Several queues may be used or filled when the command queueing arrangement 332 performs arbiter activities.” Para 0062 and FIG. 3. “In order to increase the performance of the solid state drive, the device may execute several commands in parallel.” Para 0067);
extracting first command information from a first target queue among the plurality of first command queues according to weight information corresponding to the plurality of first command queues (“the memory device may use an arbitration algorithm, such as a round-robin algorithm or a weighted round-robin algorithm. These algorithms may determine the order in which to fetch commands from multiple submission queues as well as administrative queues.” Para 0036 and FIGS. 1 and 2);
performing information format processing on the first command information to generate second command information (“When commands are received from the submission queues 308 … a doorbell time stamp may be attached by a doorbell time stamp arrangement 336 to aid in the command arbitration 330 ….” Para 0062 and FIG. 3);
distributing the second command information to a second target queue among the plurality of second command queues to wait for execution by the rewritable non-volatile memory module (“The commands are arbitrated according to a selected scheme, and then sent to command queueing 332 through the PCIe MAC PHY interconnection 326. Several queues may be used or filled when the command queueing arrangement 332 performs arbiter activities.” Para 0062 and FIG. 3).
Benisty discloses all of the claim limitations from above, but does not explicitly teach “from a flash translation layer”.
However, in an analogous art in the same field of endeavor, Choi teaches from a flash translation layer (“The user device 2000 … manages a FTL [Flash Translation Layer] on the host 2100, and if a specific condition is satisfied, the user device 2000 sends a read hint command to the storage device 2200 prior to a transfer of a read command.” Para 0136 and FIG. 2. See CMD queue 2131 in FIG. 2).
Given the teaching of Choi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty with “from a flash translation layer”. The motivation would be that a storage device may improve program/read performance using page offset in a read hint command from a host, para 0136 of Choi.
As per dependent claim 2, Benisty in combination with Choi discloses the method of claim 1. Benisty teaches further comprising: setting a weight value corresponding to each of the plurality of first command queues according to the number of command information cached in each of the plurality of first command queues (“Referring to FIG. 2, an NVMe [Non Volatile Memory Express] Weighted Round Robin (WRR) arbiter is illustrated. … commands are broken into urgent, high priority, medium priority, low priority and an ASQ section. ASQ's proceed under strict priority 1, …. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority.” Para 0050 and FIG. 2).
As per dependent claim 3, Benisty in combination with Choi discloses the method of claim 1. Benisty teaches wherein the step of extracting the first command information from the first target queue among the plurality of first command queues according to the weight information corresponding to each of the plurality of first command queues comprises: in a queue selection operation, comparing weight values corresponding to each of the plurality of first command queues; and selecting one of the plurality of first command queues as the first target queue according to a comparison result (“Referring to FIG. 2, an NVMe Weighted Round Robin (WRR) arbiter is illustrated. … commands are broken into urgent, high priority, medium priority, low priority and an ASQ section. ASQ's proceed under strict priority 1, the highest priority possible. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority. Etc.” Para 0050 and FIG. 2).
As per claims 9-11, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-3. “A method and apparatus for operating a solid state drive is disclosed” para 0008 of Benisty.
Claims 4, 8, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Zhu et al. US 2021/0019085 (“Zhu”).
As per dependent claim 4, Benisty in combination with Choi discloses the method of claim 3. Benisty may not explicitly disclose, but in an analogous art in the same field of endeavor, Zhu teaches further comprising: in response to a first candidate queue among the plurality of first command queues being selected as the first target queue for multiple consecutive times, updating a count value corresponding to the first candidate queue; and in response to the count value satisfying a predetermined condition, marking the first candidate queue so that the first candidate queue is excluded in the next queue selection operation (“At operation 720, the processing logic determines a difference value between the quota of commands and a count of commands previously selected from the respective queue … At operation 730, the processing logic determines … by excluding any queue … having a negative number for the respective difference value ….” Para 0098 and FIG. 7).
Given the teaching of Zhu, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty and Choi with “further comprising: in response to a first candidate queue among the plurality of first command queues being selected as the first target queue for multiple consecutive times, updating a count value corresponding to the first candidate queue; and in response to the count value satisfying a predetermined condition, marking the first candidate queue so that the first candidate queue is excluded in the next queue selection operation”. The motivation would be that a worst case latency can be improved using quota, para 0015 of Zhu.
As per dependent claim 8, Benisty in combination with Choi discloses the method of claim 1. Benisty teaches wherein the rewritable non-volatile memory module comprises a plurality of memory chips (“multiple two dimensional memory arrays or three dimensional memory arrays may be formed on separate chips and then packaged together to form a stacked-chip memory device.” Para 0080).
Benisty may not explicitly disclose, but in an analogous art in the same field of endeavor, Zhu teaches and the first target queue and the second target queue correspond to the same memory chip among the plurality of memory chips (“The controller 115 manages a number of queues 202-208 within the controller 115” para 0027 and FIG. 2).
Given the teaching of Zhu, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty and Choi with “and the first target queue and the second target queue correspond to the same memory chip among the plurality of memory chips”. The motivation would be that the command queues can improve request traffic throughput, para 0024 of Zhu.
As per dependent claims 12 and 16, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 4 and 8.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Zhu and in further view of Matveyenko et al. US 2022/0253249 (“Matveyenko”).
As per dependent claim 5, Benisty in combination with Choi and Zhu discloses the method of claim 4. Benisty, Choi, and Zhu may not explicitly disclose, but in an analogous art in the same field of endeavor, Matveyenko teaches further comprising: in response to the first candidate queue not being selected as the first target queue for consecutive times, resetting the count value corresponding to the first candidate queue (“the command could be considered starved when the age counter reaches zero” para 0038).
Given the teaching of Matveyenko, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty, Choi, Zhu with “further comprising: in response to the first candidate queue not being selected as the first target queue for consecutive times, resetting the count value corresponding to the first candidate queue”. The motivation would be that age tracking can improve QoS, para 0021 of Matveyenko.
As per dependent claim 13, this claim is rejected based on arguments provided above for similar rejected dependent claim 5.
Claims 6-7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Choi and in further view of Donley et al. US 2022/0100411 (“Donley”).
As per dependent claim 6, Benisty in combination with Choi discloses the method of claim 1. Benisty teaches in response to the first target command information and at least one third target command information in the first target queue satisfying a second condition, adjusting the at least one third target command information to be sequenced after the first target command information (“ASQ's proceed under strict priority 1, the highest priority possible. Urgent SQ are sorted through a RR arbiter and are designated as strict priority 2, or the next highest possible priority.” Para 0050 and FIG. 2);
Benisty and Choi may not explicitly disclose, but in an analogous art in the same field of endeavor, Donley teaches further comprising: performing command merging on the first target queue (“identifying (402) … from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination” para 0053 and FIGS. 4-5);
in the command merging, selecting first target command information in the first target queue and traversing remaining command information in the first target queue based on the first target command information; in response to the first target command information and at least one second target command information in the first target queue satisfying a first condition, merging the first target command information and the at least one second target command information (“determining (404) … in dependence upon a set of conditions, whether two or more candidate write transactions are combinable, combining (406) … the at least two candidate write transactions into a combined write transaction,” para 0053 and FIGS. 4-5);
ending the command merging after detecting last command information (“determining (404) … in dependence upon a set of conditions, whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5. All transactions in the queue are considered) or command information with a barrier flag in the first target queue.
Given the teaching of Donley, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Benisty and Choi with “further comprising: performing command merging on the first target queue” and “in the command merging, selecting first target command information in the first target queue and traversing remaining command information in the first target queue based on the first target command information; in response to the first target command information and at least one second target command information in the first target queue satisfying a first condition, merging the first target command information and the at least one second target command information” and “ending the command merging after detecting last command information or command information with a barrier flag in the first target queue”. The motivation would be that the command queues can improve request traffic throughput, para 0024 of Zhu.
As per dependent claim 7, Benisty in combination with Choi and Donley discloses the method of claim 6. Benisty and Choi may not explicitly disclose, but Donley teaches further comprising: in response to the first target command information and the at least one second target command information belonging to a same type of commands (“determining (404) … whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5) and the first target command information and the at least one second target command information corresponding to a same memory page or different memory planes, determining that the first target command information and the at least one second target command information satisfy the first condition (“two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction also includes determining (504) whether an offset entry of the incoming write transaction and an offset entry of the existing write transaction are consecutive.” Para 0055);
in response to the first target command information and the at least one third target command information belonging to the same type of commands (“determining (404) … whether two or more candidate write transactions are combinable,” para 0053 and FIGS. 4-5) and the first target command information and the at least one third target command information corresponding to a plurality of consecutive memory pages, determining that the first target command information and the at least one third target command information satisfy the second condition (“two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction also includes determining (504) whether an offset entry of the incoming write transaction and an offset entry of the existing write transaction are consecutive.” Para 0055).
The same motivation that was utilized for combining Benisty and Donley as set forth in claim 6 is equally applicable to claim 7.
As per dependent claims 14-15, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 6-7.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132