DETAILED ACTION
1. This Office Action is taken in response to Applicants’ application 18/929,602 filed on 10/28/2024.
Claims 1-20 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In response to the amendments and remarks, an updated claim analysis has been made. Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
5. Claims 1-20 are rejected under the judicially created doctrine of obvious-type double patenting as being unpatentable over independent claims 1-20 of US Patent 12,131,066. Although not all of the conflicting claims are exactly identical, they are extremely similar and are not patentably distinct from each other as shown in the example below:
18/929,602
12,131,066
1. A system comprising: a memory device configured with a zoned namespace having a plurality of zones, wherein each zone is associated with a respective zone identifier; and a processing device, operatively coupled with the memory device, to perform operations comprising: storing, in a first queue of the memory device, a first identifier of a first memory access operation to be performed at a first zone of the memory device; identifying one of a plurality of plane sets of the memory device that is associated with the first zone of the memory device; identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set; responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving, from the second queue, a second identifier of a second memory access operation to be performed at a second zone of the memory device; storing the second identifier of the second memory access operation in a third queue of the memory device, wherein the third queue corresponds to a second plane set of the memory device; and performing the second memory access operation at the second zone associated with the second plane set of the memory device.
1. A system comprising: a memory device configured with a zoned namespace having a plurality of zones, wherein each zone is associated with a respective zone identifier; and a processing device, operatively coupled with the memory device, to perform operations comprising: storing a first identifier of a first memory access operation in a first queue of the memory device, wherein the first queue comprises one or more entries, wherein each entry stores an identifier of a memory access operation, and wherein the first memory access operation is to be performed at a first zone of the memory device; identifying, among a plurality of plane sets of the memory device, a plane set that is associated, by a memory data structure, with the first zone of the memory device; identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set, wherein the second queue comprises one or more entries, wherein each entry stores an identifier of a memory access operation to be performed at the first zone of the memory device; responsive to determining that a number of identifiers of memory access operations stored in the second queue is greater than a threshold number of identifiers of memory access operations that can be stored in the second queue, retrieving a second identifier of a second memory access operation from the first queue, wherein the second memory access operation is to be performed at a second zone of the memory device; storing the second identifier of the second memory access operation in a third queue of the memory device, wherein the third queue corresponds to a second plane set of the memory device, wherein the second plane set is associated with the second zone of the memory device; and performing the second memory access operation at the second zone of the memory device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Inbar et al. (US Patent Application Publication 2021/0389879, hereinafter Inbar), and in view of Sang et al. (US Patent 6,401,147, hereinafter Sang).
As to claim 1, Inbar teaches A system [as shown in figure 1] comprising:
a memory device configured with a zoned namespace having a plurality of zones
[as shown in figures 11, 14, and 16; … A particular example discussed below is of a use case for “Zoned Namespace Storage”, or ZNS… (¶ 0101-0104)], wherein each zone is associated with a respective zone identifier [as shown in figures 11, 14, and 16]; and
a processing device, operatively coupled with the memory device [as shown in figure 1, with controller (102) and memory package (104)], to perform operations comprising:
storing, in a first queue of the memory device, a first identifier of a first memory access operation to be performed at a first zone of the memory device [the corresponding first queue comprises write queues, figure 16, 1655 and 1657; FIG. 14 represents the memory die after a sequence of four different examples of write operations. In a first write operation, only Zone A data is programmed, starting at the initial point on word line WL0 and across all five fingers of both Plane 0 and Plane 1. In this first write operation, no Zone B data is written and all of word line WL0 is used in planes Plane 0 and Plane 1, which are written in parallel. In a second write operation, data is concurrently written for both Zone A and Zone B, but to different word lines, with Zone A data being written to all fingers of Plane 0 and Plane 1 along word line WL1 and Zone B data being written to all fingers of Plane 2 and Plane 3 along word line WL0. In a third write operation, only Zone B data is written and only to a partial plane of fingers 0 and 1 of Plane 2 along word line WL1. In a fourth write operation, data is concurrently written to both zones, but at different word lines and different sets of fingers … (¶ 0114); … The host interface/processor 1653 stores the Zone A and Zone B data in different queues, a Zone A write queue 1655 and a Zone B write queue 1657. For example, in the more detailed representation of FIG. 3 these queues can be held in the buffer 232/262. The Zone A write queue 1655 can be used to aggregate Zone A data as it comes in from the host 1600 and the Zone B write queue 1657 can be used to aggregate Zone B data as it comes in from the host 1600 … (¶ 0122); Sang also teaches a first queue -- A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract)];
identifying one of a plurality of plane sets of the memory device that is associated with the first zone of the memory device [as shown in figures 14-16; For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die (abstract)];
identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set [as shown in figure 16, where the corresponding second queue comprises page buffers (1663); … For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines. To write the Zone A and Zone B data from queues 1655 and 1657 into the memory die 1682, the data can be formed into pages or partial pages in the buffer 1659, that in some embodiments can correspond to the buffers 228/258. Once the pages, or partial pages, of data are assembled, the data is transmitted over the memory bus 1694 along with the assigned physical addresses … (¶ 0122-0124); Sang also teaches a second queue -- A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract)];
responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving, from the second queue, a second identifier of a second memory access operation to be performed at a second zone of the memory device [… The Zone A write queue 1655 can be used to aggregate Zone A data as it comes in from the host 1600 and the Zone B write queue 1657 can be used to aggregate Zone B data as it comes in from the host 1600. For writing the Zone A and Zone B data into the memory array 1684 of the memory die 1682, the controller 1651 combines the data from Zone A and Zone B to be written concurrently into a page of data, or, if the combined data to be written from each of Zone A and Zone B is less than a full page, a partial page of data. For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines. To write the Zone A and Zone B data from queues 1655 and 1657 into the memory die 1682, the data can be formed into pages or partial pages in the buffer 1659, that in some embodiments can correspond to the buffers 228/258. Once the pages, or partial pages, of data are assembled, the data is transmitted over the memory bus 1694 along with the assigned physical addresses … (¶ 0122-0124);
Sang more expressively teaches this limitation -- A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract); … The first queue area and the second queue areas each include an input portion and an output portion. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using either a trickle mode or an overflow mode, based on a prescribed threshold value. Depending on the specific system, the threshold value used by the queue overflow engine may correspond to the number of entries stored in the first queue area, the number of entries stored in the second queue area, or both (c2 L54 to c3 L2); … The queue overflow engine thus monitors the number of entries currently stored in the first and second queue areas. If the first queue area is empty, then the queue overflow engine refrains from transferring entries from the overflow storage area until a minimum threshold value is reached in the second queue area. If additional entries are input to the first queue area before the minimum threshold value is reached, then entries are transferred to the second queue area directly from the first queue area using the trickle mode … According to one embodiment of the invention, the trickle mode requires that entries be transferred directly to the second queue area if there is available capacity in the second queue area in order to minimize latency. If there is no available capacity in the second queue area, then the entries are transferred to an overflow storage area in order to maximize the storage capacity of the queue structure (c3 L14-59); Under normal conditions, entries are transferred from the first queue area to the second queue area as quickly as possible. The second queue area corresponds to the queue read side previously described. Whenever there are entries in the first queue area, the status of the second queue area is examined in order to determine whether the entries in the first queue area may be transferred to the second queue area. For example, at step S716, the queue overflow engine determines whether or not the second queue area is full (i.e., unable to accept any additional entries). If the second queue area is full, then the status of the first queue area is examined. At step S718, the queue overflow engine determines if the first queue area is also full. If the first queue area is not full, then control returns to step S710 in order to await the arrival of new entries. If the first queue area is full, then one or more entries are transferred from the first queue area to the overflow storage area at step S720. Control is then returned to step S710 (c14 L60 to c15 L10); If the second queue area is not full, then at step S722, entries are transferred from the first queue area directly to the second queue area. The queue overflow engine determines the number of entries to transfer to the second queue area by continually monitoring the status of both the first queue area and the second queue area … This sequence is repeated until the first queue area is empty or the second queue area is full … At step S726, the queue overflow engine determines if the number of entries in the second queue area is below a second threshold value. The second threshold value corresponds to a minimum number of entries that the queue overflow engine assigns to the second queue area … if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L31 to c16 L6)];
storing the second identifier of the second memory access operation in a third queue of the memory device, wherein the third queue corresponds to a second plane set of the memory device [this limitation is taught by Sang -- A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract); … The first queue area and the second queue areas each include an input portion and an output portion. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using either a trickle mode or an overflow mode, based on a prescribed threshold value. Depending on the specific system, the threshold value used by the queue overflow engine may correspond to the number of entries stored in the first queue area, the number of entries stored in the second queue area, or both (c2 L54 to c3 L2); … The queue overflow engine thus monitors the number of entries currently stored in the first and second queue areas. If the first queue area is empty, then the queue overflow engine refrains from transferring entries from the overflow storage area until a minimum threshold value is reached in the second queue area. If additional entries are input to the first queue area before the minimum threshold value is reached, then entries are transferred to the second queue area directly from the first queue area using the trickle mode … According to one embodiment of the invention, the trickle mode requires that entries be transferred directly to the second queue area if there is available capacity in the second queue area in order to minimize latency. If there is no available capacity in the second queue area, then the entries are transferred to an overflow storage area in order to maximize the storage capacity of the queue structure (c3 L14-59); Under normal conditions, entries are transferred from the first queue area to the second queue area as quickly as possible. The second queue area corresponds to the queue read side previously described. Whenever there are entries in the first queue area, the status of the second queue area is examined in order to determine whether the entries in the first queue area may be transferred to the second queue area. For example, at step S716, the queue overflow engine determines whether or not the second queue area is full (i.e., unable to accept any additional entries). If the second queue area is full, then the status of the first queue area is examined. At step S718, the queue overflow engine determines if the first queue area is also full. If the first queue area is not full, then control returns to step S710 in order to await the arrival of new entries. If the first queue area is full, then one or more entries are transferred from the first queue area to the overflow storage area at step S720. Control is then returned to step S710 (c14 L60 to c15 L10); If the second queue area is not full, then at step S722, entries are transferred from the first queue area directly to the second queue area. The queue overflow engine determines the number of entries to transfer to the second queue area by continually monitoring the status of both the first queue area and the second queue area … This sequence is repeated until the first queue area is empty or the second queue area is full … At step S726, the queue overflow engine determines if the number of entries in the second queue area is below a second threshold value. The second threshold value corresponds to a minimum number of entries that the queue overflow engine assigns to the second queue area … if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L31 to c16 L6); Inbar -- … For writing the Zone A and Zone B data into the memory array 1684 of the memory die 1682, the controller 1651 combines the data from Zone A and Zone B to be written concurrently into a page of data, or, if the combined data to be written from each of Zone A and Zone B is less than a full page, a partial page of data. For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines … On the memory die 1682, the (partial or full) pages of data can be stored in a write, or page, buffer 1663. The write buffer 1663 is used to hold the data to be programmed into the memory array and is commonly referred to as a page buffer, where this terminology is used in the following discussion, but it will be understood that in partial page writes (i.e., where less than all of the bit lines, fingers, and/or planes are written), the page buffer will hold less than a full page of data … (¶ 0122-0123)]; and
performing the second memory access operation at the second zone associated with the second plane set of the memory device [… The Zone A write queue 1655 can be used to aggregate Zone A data as it comes in from the host 1600 and the Zone B write queue 1657 can be used to aggregate Zone B data as it comes in from the host 1600. For writing the Zone A and Zone B data into the memory array 1684 of the memory die 1682, the controller 1651 combines the data from Zone A and Zone B to be written concurrently into a page of data, or, if the combined data to be written from each of Zone A and Zone B is less than a full page, a partial page of data. For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines. To write the Zone A and Zone B data from queues 1655 and 1657 into the memory die 1682, the data can be formed into pages or partial pages in the buffer 1659, that in some embodiments can correspond to the buffers 228/258. Once the pages, or partial pages, of data are assembled, the data is transmitted over the memory bus 1694 along with the assigned physical addresses … (¶ 0122-0124)].
Regarding claim 1, Inbar teaches retrieving and combining memory access operations from both the first queue and the second queue to form a full page [… The Zone A write queue 1655 can be used to aggregate Zone A data as it comes in from the host 1600 and the Zone B write queue 1657 can be used to aggregate Zone B data as it comes in from the host 1600. For writing the Zone A and Zone B data into the memory array 1684 of the memory die 1682, the controller 1651 combines the data from Zone A and Zone B to be written concurrently into a page of data, or, if the combined data to be written from each of Zone A and Zone B is less than a full page, a partial page of data. For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines. To write the Zone A and Zone B data from queues 1655 and 1657 into the memory die 1682, the data can be formed into pages or partial pages in the buffer 1659, that in some embodiments can correspond to the buffers 228/258. Once the pages, or partial pages, of data are assembled, the data is transmitted over the memory bus 1694 along with the assigned physical addresses … (¶ 0122-0124)], but does not expressively teach responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving the identifier of the memory access operation from the first queue; storing the identifier of the memory access operation in the second queue.
However, Sang specifically teaches responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving the identifier of the memory access operation from the first queue; storing the identifier of the memory access operation in the second queue [A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract); … The first queue area and the second queue areas each include an input portion and an output portion. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using either a trickle mode or an overflow mode, based on a prescribed threshold value. Depending on the specific system, the threshold value used by the queue overflow engine may correspond to the number of entries stored in the first queue area, the number of entries stored in the second queue area, or both (c2 L54 to c3 L2); … The queue overflow engine thus monitors the number of entries currently stored in the first and second queue areas. If the first queue area is empty, then the queue overflow engine refrains from transferring entries from the overflow storage area until a minimum threshold value is reached in the second queue area. If additional entries are input to the first queue area before the minimum threshold value is reached, then entries are transferred to the second queue area directly from the first queue area using the trickle mode … According to one embodiment of the invention, the trickle mode requires that entries be transferred directly to the second queue area if there is available capacity in the second queue area in order to minimize latency. If there is no available capacity in the second queue area, then the entries are transferred to an overflow storage area in order to maximize the storage capacity of the queue structure (c3 L14-59); Under normal conditions, entries are transferred from the first queue area to the second queue area as quickly as possible. The second queue area corresponds to the queue read side previously described. Whenever there are entries in the first queue area, the status of the second queue area is examined in order to determine whether the entries in the first queue area may be transferred to the second queue area. For example, at step S716, the queue overflow engine determines whether or not the second queue area is full (i.e., unable to accept any additional entries). If the second queue area is full, then the status of the first queue area is examined. At step S718, the queue overflow engine determines if the first queue area is also full. If the first queue area is not full, then control returns to step S710 in order to await the arrival of new entries. If the first queue area is full, then one or more entries are transferred from the first queue area to the overflow storage area at step S720. Control is then returned to step S710 (c14 L60 to c15 L10); If the second queue area is not full, then at step S722, entries are transferred from the first queue area directly to the second queue area. The queue overflow engine determines the number of entries to transfer to the second queue area by continually monitoring the status of both the first queue area and the second queue area … This sequence is repeated until the first queue area is empty or the second queue area is full … At step S726, the queue overflow engine determines if the number of entries in the second queue area is below a second threshold value. The second threshold value corresponds to a minimum number of entries that the queue overflow engine assigns to the second queue area … if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L31 to c16 L6)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to retrieve the identifier of the memory access operation from the first queue; storing the identifier of the memory access operation in the second queue responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, as specifically demonstrated by Sang, and to incorporate it into the existing scheme disclosed by Inbar, because Sang teaches doing this would reduce data transferring and accessing latency [… In most systems, it is desirable that the queues have low latencies so that processing of an entry is not delayed very long due to delays caused by the queues themselves. A low queue latency means that an entry will flow from the entrance to the queue to the exit of the queue quickly, in comparison to queues with higher latencies. One factor that has a significant impact on the latency of a queue is the length, or capacity, of the queue. The greater the capacity of the queue to store entries, the higher the latency of the queue (c1 L53-62)].
As to claim 2, Inbar in view of Sang teaches The system of claim 1, wherein the threshold criterion is satisfied when the number of identifiers of memory access operations stored in the second queue is greater than a threshold number of identifiers of memory access operations [Sang -- According to one embodiment of the present invention, the number of entries in the second queue area is allowed to decrease (i.e., retrieved from the queue structure) for a prescribed time interval while waiting for entries to be input to the first queue area … As illustrated in FIG. 7, if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L56 to c16 L6)].
As to claim 3, Inbar in view of Sang teaches The system of claim 1, wherein the operations further comprise: responsive to determining that the number of identifiers of memory access operations stored in the second queue does not satisfy the threshold criterion, retrieving the first identifier of the first memory access operation from the first queue; and storing the first identifier of the first memory access operation in the second queue [Sang -- According to one embodiment of the present invention, the number of entries in the second queue area is allowed to decrease (i.e., retrieved from the queue structure) for a prescribed time interval while waiting for entries to be input to the first queue area … As illustrated in FIG. 7, if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L56 to c16 L6)].
As to claim 4, Inbar in view of Sang teaches The system of claim 1, wherein the operations further comprise: receiving, from a host system, a request to perform the second memory access operation at the second zone of the memory device; storing the second identifier of the second memory access operation in the first queue of the memory device; identifying, among the plurality of plane sets of the memory device, the second plane set that is associated, by a memory data structure, with the second zone of the memory device; determining that a number of identifiers of memory access operations stored in the third queue is less than the threshold number of identifiers of memory access operations; responsive to determining that the number of identifiers of memory access operations stored in the third queue is less than the threshold number of identifiers of memory access operations, retrieving the second identifier of the second memory access operation from the first queue; and storing the second identifier of the second memory access operation in the third queue [Sang -- A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure (abstract); … The first queue area and the second queue areas each include an input portion and an output portion. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using either a trickle mode or an overflow mode, based on a prescribed threshold value. Depending on the specific system, the threshold value used by the queue overflow engine may correspond to the number of entries stored in the first queue area, the number of entries stored in the second queue area, or both (c2 L54 to c3 L2); … The queue overflow engine thus monitors the number of entries currently stored in the first and second queue areas. If the first queue area is empty, then the queue overflow engine refrains from transferring entries from the overflow storage area until a minimum threshold value is reached in the second queue area. If additional entries are input to the first queue area before the minimum threshold value is reached, then entries are transferred to the second queue area directly from the first queue area using the trickle mode … According to one embodiment of the invention, the trickle mode requires that entries be transferred directly to the second queue area if there is available capacity in the second queue area in order to minimize latency. If there is no available capacity in the second queue area, then the entries are transferred to an overflow storage area in order to maximize the storage capacity of the queue structure (c3 L14-59); Under normal conditions, entries are transferred from the first queue area to the second queue area as quickly as possible. The second queue area corresponds to the queue read side previously described. Whenever there are entries in the first queue area, the status of the second queue area is examined in order to determine whether the entries in the first queue area may be transferred to the second queue area. For example, at step S716, the queue overflow engine determines whether or not the second queue area is full (i.e., unable to accept any additional entries). If the second queue area is full, then the status of the first queue area is examined. At step S718, the queue overflow engine determines if the first queue area is also full. If the first queue area is not full, then control returns to step S710 in order to await the arrival of new entries. If the first queue area is full, then one or more entries are transferred from the first queue area to the overflow storage area at step S720. Control is then returned to step S710 (c14 L60 to c15 L10); If the second queue area is not full, then at step S722, entries are transferred from the first queue area directly to the second queue area. The queue overflow engine determines the number of entries to transfer to the second queue area by continually monitoring the status of both the first queue area and the second queue area … This sequence is repeated until the first queue area is empty or the second queue area is full … At step S726, the queue overflow engine determines if the number of entries in the second queue area is below a second threshold value. The second threshold value corresponds to a minimum number of entries that the queue overflow engine assigns to the second queue area … if the number of entries in the second queue area is above the second threshold value, then control returns to step S724, where the status of the first queue area is determined. If the number of entries in the second queue area is less than the second threshold value, then control passes to step S728. According to steps S724 and S726 of the disclosed embodiment, the second threshold value corresponds to a minimum number of entries that the queue overflow engine determines to be allowable within the second queue area while the status of the first queue area is determined (c15 L31 to c16 L6); Inbar -- … For writing the Zone A and Zone B data into the memory array 1684 of the memory die 1682, the controller 1651 combines the data from Zone A and Zone B to be written concurrently into a page of data, or, if the combined data to be written from each of Zone A and Zone B is less than a full page, a partial page of data. For example, in the examples of writes given in FIG. 14, only the second write is a full page of data spanning all fingers of all four planes, albeit on different word lines … On the memory die 1682, the (partial or full) pages of data can be stored in a write, or page, buffer 1663. The write buffer 1663 is used to hold the data to be programmed into the memory array and is commonly referred to as a page buffer, where this terminology is used in the following discussion, but it will be understood that in partial page writes (i.e., where less than all of the bit lines, fingers, and/or planes are written), the page buffer will hold less than a full page of data … (¶ 0122-0123)].
As to claim 5, Inbar in view of Sang teaches The system of claim 1, wherein the operations further comprise: identifying a logical block address (LBA) associated with the first memory access operation; and determining, using the LBA, the respective zone identifier [Inbar -- FIG. 11 illustrates a division of a device's logical block address (LBA) range into zones. As illustrated in FIG. 11, a range of LBAs for host data is divided up into (X+1) zones, where data is stored based upon zones and a zone contains a set amount of data. As illustrated in the detail of the expanded zone, writes of data within a zoned namespace are based upon a write position pointer, with each zones having an independent write pointer, such as illustrated in the detail of FIG. 11. Write commands advance the write pointer and a zone reset command rewinds the zone's pointer (¶ 0103)].
As to claim 6, Inbar in view of Sang teaches The system of claim 1, wherein the operations are performed by a hardware accelerator [Inbar -- … The processor can be any standard processor known in the art. The data path controllers 222/252 can be a processor, FPGA, microprocessor or other type of controller. The XOR engines 224/254 and ECC engines 226/256 are dedicated hardware circuits, known as hardware accelerators. In other embodiments, the XOR engines 224/254 and ECC engines 226/256 can be implemented in software. The scheduler, buffer, and TM Interfaces are hardware circuits (¶ 0034)].
As to claim 7, Inbar in view of Sang teaches The system of claim 1, wherein each zone of the plurality of zones comprises a plurality of blocks residing on a plurality of planes of a die of the memory device [Inbar -- as shown in figures 11 and 14; For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die (abstract)].
As to claim 8, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 9, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
As to claim 10, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 11, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 12, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 14, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 18, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
Conclusion
7. Claims 1-20 are rejected as explained above.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached on 571-272-9779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/SHENG JEN TSAI/Primary Examiner, Art Unit 2136
December 28, 2025