DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “…a reset pulse simulation circuit to output a rising reset signal and a falling reset signal having a pulse width corresponding to pulse widths of the voltage rising signal and the voltage falling signal output from the phase frequency comparator…”
It is unclear how this limitation is to be interpreted, e.g.,
the voltage rising signal and rising reset signal have an equal pulse width and the voltage falling signal and falling reset signal have an equal pulse width;
the voltage rising signal, rising reset signal, voltage falling signal and falling reset signal have equal pulse widths; or
the reset pulse simulation circuit outputs a rising reset signal and a falling reset signal, the falling reset signal having a pulse width corresponding to pulse widths of the voltage rising signal and the voltage falling signal (i.e., the rising reset signal is not required to have a pulse width corresponding to the voltage rising signal or the voltage falling signal).
Furthermore, it is unclear whether “when a phase difference between the reference clock signal and the feedback clock signal is zero every time the phase frequency comparator completes outputting of the voltage rising signal and the voltage falling signal” should be interpreted, e.g.,
In response to the phase difference between the reference clock and feedback clock being zero, the reset pulse simulation circuit outputs the rising reset signal and the falling reset signal
A phase frequency comparator outputs, during each of a plurality phase comparison cycles, a voltage rising signal and a voltage falling signal, wherein the phase comparison cycle ends when the phase difference between the reference clock signal and the feedback clock signal is zero.
For the purposes of examination and in accordance with [0016]-[0017] of Applicant’s Specification, examiner will interpret the scope of claim 1 as follows:
A phase comparator comprising:
a phase frequency comparator to compare phases of a reference clock signal and a feedback clock signal for a plurality of phase comparison cycles and output both of a voltage rising signal and a voltage falling signal once per phase comparison cycle based upon the phase comparison;
a reset pulse simulation circuit to output a rising reset signal and a falling reset signal, wherein the pulse width of the rising reset signal is substantially equal to a minimum pulse width of the voltage rising signal and the pulse width of the falling reset signal is substantially equal to a minimum pulse width of the voltage falling signal, wherein the minimum pulse widths correspond to a phase difference between the reference clock signal and the feedback clock signal being zero,
a charge pump circuit to output a first current on a basis of the voltage rising signal and the voltage falling signal output from the phase frequency comparator, and output a second current on a basis of the rising reset signal and the falling reset signal output from the reset pulse simulation circuit; and
a current output circuit having a capacitor capable of being charged with a charge in accordance with the first current output from the charge pump circuit and a charge in accordance with the second current output from the charge pump circuit, the current output circuit being to output a current based on a difference between the charge in accordance with the first current and the charge in accordance with the second current that are charged in the capacitor.
Allowable Subject Matter
Claims 2, 5-6 and 8 are allowed. Specifically, the claim limitation of “a charge pump circuit to output a first current on a basis of the voltage rising signal and the voltage falling signal output on a basis of a phase difference of signals included in the first signal pair, and output a second current on a basis of the voltage rising signal and the voltage falling signal output on a basis of a phase difference of signals included in the second signal pair” was not found in the prior art.
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Specifically, the claim limitation of “reset pulse simulation circuit to output a rising reset signal and a falling reset signal having a pulse width corresponding to pulse widths of the voltage rising signal and the voltage falling signal output from the phase frequency comparator when a phase difference between the reference clock signal and the feedback clock signal is zero every time the phase frequency comparator completes outputting of the voltage rising signal and the voltage falling signal” was not found in the prior art.
Claims 3-4 and 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kobayashi (US 2006/0119405) teaches a PLL circuit having a delay adjustment for resetting UP and DOWN signals but fails to teach the limitations cited above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849