DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. US 12210426 B2 (reference patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the claimed scope of the instant application is broader than the reference patent, which comprises limitation of weighted anatomical features. Therefore, the reference patent anticipates the instant application.
The following table illustrates the conflicting claim pairs:
Instant Application
1
2
3
4
5
6
7
8
9
10
11
12
Reference Patent
1 & 3
4
6
7
8
9
1 & 5
4
6
7
8
9
Claims of the instant application are compared to claims of Reference Patent in the following tables.
Instant Application
Reference Patent
1. A control system configured to control a head-up display, comprising:
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display;
a first error detection circuit configured to perform first error detection on the second image data;
a first error code value generation circuit configured to generate a first error code value based on the second image data;
a transmission interface circuit configured to transmit the second image data;
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit;
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit;
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value; and
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection,
1. A control system configured to control a head-up display, comprising:
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display;
a first error detection circuit configured to perform first error detection on the second image data;
a first error code value generation circuit configured to generate a first error code value based on the second image data;
a transmission interface circuit configured to transmit the second image data;
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit;
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit;
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value; and
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection,
wherein the second error detection relates to a property with respect to a communication of the second image data between the transmission interface circuit and the reception interface circuit.
wherein the first error detection circuit is configured to
convert the second image data into third image data by inverse mapping processing of the mapping processing, and
perform the first error detection by comparing the first image data with the third image data.
3. The control system according to claim 1, wherein
the first error detection circuit is configured to
convert the second image data into third image data by inverse mapping processing of the mapping processing, and
perform the first error detection by comparing the first image data with the third image data.
Instant Application
Reference Patent
2. The control system according to claim 1, further comprising:
a first circuit device including the image processing circuit, the first error detection circuit, the first error code value generation circuit, and the transmission interface circuit; and
a second circuit device including the reception interface circuit and the second error code value generation circuit.
4. The control system according to claim 1, further comprising:
a first circuit device including the image processing circuit, the first error detection circuit, the first error code value generation circuit, and the transmission interface circuit; and
a second circuit device including the reception interface circuit and the second error code value generation circuit.
Instant Application
Reference Patent
3. The control system according to claim 1, wherein
the control circuit is configured to output the control signal for turning off a light source of the head-up display.
6. The control system according to claim 1, wherein
the control circuit is configured to output the control signal for turning off a light source of the head-up display.
Instant Application
Reference Patent
4. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data before being transmitted by the transmission interface circuit based on the control signal.
7. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data before being transmitted by the transmission interface circuit based on the control signal.
Instant Application
Reference Patent
5. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data received by the reception interface circuit based on the control signal.
8. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data received by the reception interface circuit based on the control signal.
Instant Application
Reference Patent
6. An electronic apparatus, comprising:
the control system according to claim 1; and
the head-up display.
9. An electronic apparatus, comprising:
the control system according to claim 1; and
the head-up display.
Instant Application
Reference Patent
7. A control system configured to control a head-up display, comprising:
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display;
a first error detection circuit configured to perform first error detection on the second image data;
a first error code value generation circuit configured to generate a first error code value based on the second image data;
a transmission interface circuit configured to transmit the second image data;
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit;
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit;
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value;
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection;
1. A control system configured to control a head-up display, comprising:
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display;
a first error detection circuit configured to perform first error detection on the second image data;
a first error code value generation circuit configured to generate a first error code value based on the second image data;
a transmission interface circuit configured to transmit the second image data;
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit;
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit;
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value; and
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection,
wherein the second error detection relates to a property with respect to a communication of the second image data between the transmission interface circuit and the reception interface circuit.
and
a third error detection circuit,
wherein the image processing circuit includes:
a storage circuit storing the first image data; and
an image conversion circuit configured to perform the mapping processing to map the first image data stored in the storage circuit to the second image data,
the image conversion circuit is configured to
output a reference coordinate indicating a pixel position on the first image data, and output the second image data based on pixel data of the reference coordinate read from the storage circuit based on the output reference coordinate,
the third error detection circuit is configured to
perform third error detection on the reference coordinate output by the image conversion circuit, and
the control circuit is configured to
output the control signal when an error is detected in at least one of the first error detection, the second error detection, and the third error detection.
5. The control system according to claim 1, further comprising:
a third error detection circuit, wherein
the image processing circuit includes:
a storage circuit storing the first image data; and
an image conversion circuit configured to perform the mapping processing to map the first image data stored in the storage circuit to the second image data,
the image conversion circuit is configured to
output a reference coordinate indicating a pixel position on the first image data, and output the second image data based on pixel data of the reference coordinate read from the storage circuit based on the output reference coordinate,
the third error detection circuit is configured to
perform third error detection on the reference coordinate output by the image conversion circuit, and
the control circuit is configured to
output the control signal when an error is detected in at least one of the first error detection, the second error detection, and the third error detection.
Instant Application
Reference Patent
8. The control system according to claim 7, further comprising:
a first circuit device including the image processing circuit, the first error detection circuit, the first error code value generation circuit, and the transmission interface circuit; and
a second circuit device including the reception interface circuit and the second error code value generation circuit.
4. The control system according to claim 1, further comprising:
a first circuit device including the image processing circuit, the first error detection circuit, the first error code value generation circuit, and the transmission interface circuit; and
a second circuit device including the reception interface circuit and the second error code value generation circuit.
Instant Application
Reference Patent
9. The control system according to claim 7, wherein
the control circuit is configured to output the control signal for turning off a light source of the head-up display.
6. The control system according to claim 1, wherein
the control circuit is configured to output the control signal for turning off a light source of the head-up display.
Instant Application
Reference Patent
10. The control system according to claim 7, further comprising:
a mask circuit configured to perform mask processing on the second image data before being transmitted by the transmission interface circuit based on the control signal.
7. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data before being transmitted by the transmission interface circuit based on the control signal.
Instant Application
Reference Patent
11. The control system according to claim 7, further comprising:
a mask circuit configured to perform mask processing on the second image data received by the reception interface circuit based on the control signal.
8. The control system according to claim 1, further comprising:
a mask circuit configured to perform mask processing on the second image data received by the reception interface circuit based on the control signal.
Instant Application
Reference Patent
12. An electronic apparatus, comprising:
the control system according to claim 7; and
the head-up display.
9. An electronic apparatus, comprising:
the control system according to claim 1; and
the head-up display.
Allowable Subject Matter
Claims 1-12 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, ANAND teaches a control system configured to control a head-up display, comprising (ANAND [0005] Since head-up displays are displays for superimposing information over a user's field of vision, an image having a size and luminance that enable visual recognition of the background of a head-up display is usually displayed on the head-up display):
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display (ANAND [0053] The head-up display presents an image to the user by projecting the image onto a transparent screen, or displaying the image on a transparent display panel; [0064] The image processing circuit 140 is a circuit for realizing functions of the image processing device 520 described above. Specifically, the image processing circuit 140 performs image deformation processing for projecting images on the screen of the head-up display);
a first error detection circuit configured to perform first error detection on the second image data (ANAND] [0031] The error detection circuit 110 determines whether or not the glare index value has exceeded the first threshold value, and outputs the determination result as a first error signal SER1);
a first error code value generation circuit configured to generate a first error code value based on the second image data (ANAND] [0031] When the glare index value exceeds the first threshold value, the error detection circuit 110 activates the first error signal SER1. Upon receiving the active first error signal SER1, the processing circuit 120 performs processing corresponding to a first glare error);
a transmission interface circuit configured to transmit the second image data (ANAND] [0063] the processing device 510 transmits image data to the circuit device 100, and the interface circuit 130 receives the image data, and outputs the image data to the image processing circuit 140);
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit (ANAND [0063] The interface circuit 130 performs inter-circuit communication between the processing device 510 and the circuit device 100. Specifically, the processing device 510 transmits image data to the circuit device 100, and the interface circuit 130 receives the image data, and outputs the image data to the image processing circuit 140);
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit (ANAND [0036] the error detection circuit 110 determines whether or not the glare index value has exceeded a second threshold value, and, when it is determined that the glare index value has exceeded the second threshold value, detects the occurrence of a second glare error);
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value (ANAND [0037] the error detection circuit 110 determines whether or not the glare index value has exceeded the second threshold value, and outputs the determination result as a second error signal SER2. When the glare index value exceeds the second threshold value, the error detection circuit 110 activates the second error signal SER2); and
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection (ANAND [0039] when the occurrence of a first glare error is detected, the processing circuit 120 performs processing for notifying the host of the error. When the occurrence of a second glare error is detected, the processing circuit 120 performs display-off processing for turning off display on the head-up display).
ANAND does not but Nakano teaches
to map input first image data to second image data (Nakano [0047] A first imaging device 41 (FIGS. 1 and 2) arranged on the vehicle left side images the surroundings of the vehicle on the vehicle left side and the vehicle rear side, and transmits the imaging information to the control device 20; [0048] A second imaging device 42 (FIGS. 1 and 2) arranged on the vehicle right side images the surroundings of the vehicle on the vehicle right side and the vehicle rear side, and transmits the imaging information to the control device 20).
However, ANAND in view of Nakano does not teach
“wherein the first error detection circuit is configured to
convert the second image data into third image data by inverse mapping processing of the mapping processing, and
perform the first error detection by comparing the first image data with the third image data.“
Therefore, claim 1 as a whole is allowable.
Regarding Claim 7, ANAND teaches a control system configured to control a head-up display, comprising (ANAND [0005] Since head-up displays are displays for superimposing information over a user's field of vision, an image having a size and luminance that enable visual recognition of the background of a head-up display is usually displayed on the head-up display):
an image processing circuit configured to perform mapping processing to map input first image data to second image data to be projected onto a projection surface of the head-up display (ANAND [0053] The head-up display presents an image to the user by projecting the image onto a transparent screen, or displaying the image on a transparent display panel; [0064] The image processing circuit 140 is a circuit for realizing functions of the image processing device 520 described above. Specifically, the image processing circuit 140 performs image deformation processing for projecting images on the screen of the head-up display);
a first error detection circuit configured to perform first error detection on the second image data (ANAND] [0031] The error detection circuit 110 determines whether or not the glare index value has exceeded the first threshold value, and outputs the determination result as a first error signal SER1);
a first error code value generation circuit configured to generate a first error code value based on the second image data (ANAND] [0031] When the glare index value exceeds the first threshold value, the error detection circuit 110 activates the first error signal SER1. Upon receiving the active first error signal SER1, the processing circuit 120 performs processing corresponding to a first glare error);
a transmission interface circuit configured to transmit the second image data (ANAND] [0063] the processing device 510 transmits image data to the circuit device 100, and the interface circuit 130 receives the image data, and outputs the image data to the image processing circuit 140);
a reception interface circuit configured to receive the second image data transmitted by the transmission interface circuit (ANAND [0063] The interface circuit 130 performs inter-circuit communication between the processing device 510 and the circuit device 100. Specifically, the processing device 510 transmits image data to the circuit device 100, and the interface circuit 130 receives the image data, and outputs the image data to the image processing circuit 140);
a second error code value generation circuit configured to generate a second error code value based on the second image data received by the reception interface circuit (ANAND [0036] the error detection circuit 110 determines whether or not the glare index value has exceeded a second threshold value, and, when it is determined that the glare index value has exceeded the second threshold value, detects the occurrence of a second glare error);
a second error detection circuit configured to perform second error detection on the second image data received by the reception interface circuit, based on the first error code value and the second error code value (ANAND [0037] the error detection circuit 110 determines whether or not the glare index value has exceeded the second threshold value, and outputs the determination result as a second error signal SER2. When the glare index value exceeds the second threshold value, the error detection circuit 110 activates the second error signal SER2); and
a control circuit configured to output a control signal for turning off projection of light onto the projection surface when an error is detected in at least one of the first error detection and the second error detection (ANAND [0039] when the occurrence of a first glare error is detected, the processing circuit 120 performs processing for notifying the host of the error. When the occurrence of a second glare error is detected, the processing circuit 120 performs display-off processing for turning off display on the head-up display).
ANAND does not but Nakano teaches
to map input first image data to second image data (Nakano [0047] A first imaging device 41 (FIGS. 1 and 2) arranged on the vehicle left side images the surroundings of the vehicle on the vehicle left side and the vehicle rear side, and transmits the imaging information to the control device 20; [0048] A second imaging device 42 (FIGS. 1 and 2) arranged on the vehicle right side images the surroundings of the vehicle on the vehicle right side and the vehicle rear side, and transmits the imaging information to the control device 20).
However, ANAND in view of Nakano does not teach
“and a third error detection circuit,
wherein the image processing circuit includes:
a storage circuit storing the first image data; and
an image conversion circuit configured to perform the mapping processing to map the first image data stored in the storage circuit to the second image data,
the image conversion circuit is configured to
output a reference coordinate indicating a pixel position on the first image data, and output the second image data based on pixel data of the reference coordinate read from the storage circuit based on the output reference coordinate,
the third error detection circuit is configured to
perform third error detection on the reference coordinate output by the image conversion circuit, and
the control circuit is configured to
output the control signal when an error is detected in at least one of the first error detection, the second error detection, and the third error detection.“
Therefore, claim 7 as a whole is allowable.
The corresponding dependent claims are therefore allowable by virtue of their dependencies.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
ANAND et al. (US 20200201035 A1), referred herein as ANAND
Nakano et al. (US 20190299784 A1), referred herein as Nakano
KIKUTA et al. (US 20190013826 A1), referred herein as KIKUTA
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Samantha (Yuehan) Wang whose telephone number is (571)270-5011. The examiner can normally be reached Monday-Friday, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Samantha (YUEHAN) WANG/
Primary Examiner
Art Unit 2617
Prosecution Insights