Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. App #KR10-2024-0019063, filed on 2/7/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-11, & 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al PG Pub US 2018/0107400 A1 [hereinafter Tsai].
Regarding claims 1, 11, and 16, Tsai discloses:
a plurality of non-volatile memories (storage array 120 [0039]);
a host interface configured to receive at least one packet including a TRIM command from a host device (system interface 102 [0030]), the host interface configured to determine a trim path for processing the TRIM command by comparing a first trim range threshold value and a trim range of the TRIM command (the Flash-based block storage device may be configured to determine how to act based on the trim command matching certain triggering criteria, such as an LBA range size to be trimmed… the Flash-based block storage device may be configured to reserve the memory targeted by the trim command based on the size of the logical address range to be trimmed exceeding a threshold [0028];
a trim manage module configured to generate status data by monitoring the at least one packet, the trim manage module configured to determine the first trim range threshold value based on the status data (a threshold established by a configuration command from the host or determined algorithmically (e.g. based on historical usage and/or predicted usage) by the controller firmware algorithm [0028]); and
a processor configured to process the TRIM command based on the trim path (The device processor 108 causes the data engine 106 to delete the logical block or block range identified by the trim command 210 [0049]).
Regarding claim 8 the limitations of this claim have been noted in the rejection of claim 1. Tsai also discloses:
wherein the trim manage module is configured to generate the status data at intervals (note that this claim fails to disclose if the intervals are periodic or irregular; a threshold established by a configuration command from the host or determined algorithmically (e.g. based on historical usage and/or predicted usage) by the controller firmware algorithm [0028]).
Regarding claim 9 the limitations of this claim have been noted in the rejection of claim 1. Tsai also discloses:
wherein the status data includes a number of write commands per unit time and a number of TRIM commands per unit time (this is using the “historic usage” by the controller firmware algorithm to establish the threshold).
Regarding claim 10 the limitations of this claim have been noted in the rejection of claim 1. Tsai also discloses:
wherein the host interface is configured to transfer the at least one packet to the processor, and the trim manage module is configured to control the host interface to control the transfer of the at least one packet based on the status data (A system interface receives a trim command specifying the host logical address range. Responsive to the trim command, data in the physical address range mapped to the host logical address range is wiped, reserved, or both. Subsequent to the trim command, a write request is received for the host logical address range reserved by the trim command. The write request may be, for example, for a high-performance write operation. Responsive to the write request, and based on the reserved mapping, data specified by the write request is written to physical address range reserved by the trim command [0025]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 12, & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai, further in view of Sasaki et al. PG Pub US 2022/0011964 A1 [hereinafter Sasaki].
Regarding claims 2, 12, & 17 the limitations of these claims have been noted in the rejection of claims 1, 11, & 16. Tsai also discloses:
a buffer memory configured to store a plurality of first data (The device processor 108 may be coupled to a scratch pad memory 114 for maintaining pointers and information relating to the maintenance of user data and communication with the command handler 104, the data engine 106, a mapping table 110, or a combination thereof [0033]),
It is noted that Tsai failed to explicitly disclose:
wherein the processor is configured to detect a plurality of second data corresponding to the TRIM command among the plurality of first data based on the trim path, and process the TRIM command by invalidating the plurality of second data.
However, Sasaki discloses:
a buffer memory configured to store a plurality of first data (The cache memory 551 stores cache data such as LUT 41 and ADM 42 [0044]), wherein the processor is configured to detect a plurality of second data corresponding to the TRIM command among the plurality of first data based on the trim path, and process the TRIM command by invalidating the plurality of second data (in a case where a predetermined file is deleted in a file system used by the host, a command (hereinafter, referred to as Trim command) for invalidating the data corresponding to the file is issued from the host to the memory system [0005] When the Trim command is received by the communication interface control unit 51, the management unit 565 executes a process of updating the LUT 41 and the ADM 42 based on the Trim command [0053]).
The systems of Tsai and Sasaki are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Tsai and Sasaki since this would enable the system of Tsai to invalidate the mapping table stored in the cache based on the received trim commands. This system would “shorten the response time for the Trim command [0008].”
Regarding claims 3, 12, & 17 the limitations of these claims have been noted in the rejection of claims 1, 11, & 16. Tsai also discloses: the limitations of this claim have been noted in the rejection of claim 2. Sasaki also discloses:
wherein the trim path comprises: a range logical page number (LPN) path configured to detect the plurality of second data by entirely searching the plurality of first data (Fig. 5 Steps S21-S24 describe trimming a range of addresses [0075]-[0080]); and
a single LPN path configured to detect the plurality of second data by individually searching each of the plurality of second data among the plurality of first data (Fig. 4 Steps S11-S14 describe searching for individual LBA (LPN) to trim [0068]-[0075]).
Allowable Subject Matter
Claims 4-7, 13-15, & 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose performing the single LPN path in response to the trim range being greater than the first trim range threshold value, and performing the range LPN path in response to the trim range is smaller than the first trim range threshold value, as disclosed in claim 4.
The threshold of Tsai is used to determine the amount of Flash to be reserved as a result of the trim command, not which method of trim to be used.
The prior art of record fails to disclose wherein: the trim manage module is configured to determine whether the storage device satisfies a performance indicator for the storage device; and in response to the storage device not satisfying the performance indicator, the trim manage module is configured to determine a second trim range threshold value based on the status data, and the host interface is configured to determine the trim path based on the second trim range threshold value, as disclosed in claims 5, 14, & 19.
Although the prior art discloses each of the claimed limitations, individually, the Examiner cannot determine a reasonable motivation to combine them in the manner claimed, either in the prior art or existing case law.
Claims 6, 7, 18, & 20 are objected to for depending on objected claims, 5, 14, & 19.
Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hahn et al. PG Pub US 2024/0361957 A1 discloses memory range locking.
Knierim et al. PG Pub US 2020/0104384 A1 discloses handling continuous trim commands.
Conclusion
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/SEAN D ROSSITER/ Primary Examiner, Art Unit 2133