DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This Office Action is Non-Final.
The RCE filed 05/14/2026 is entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 12-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20130232504 A1, as previously cited, hereinafter “Yan”) in view of Duron et al. (US 20080235454 A1, hereinafter “Duron”).
Regarding Claim 1, Yan discloses a computer-implemented method of operating a processor (Fig. 14; [0092]: implemented by control circuit 18 of apparatus 10, see Fig. 1), the method comprising:
receiving, at a controller ([0092]: see above regarding control circuit 18), a first indication that a fault is detected in a processing unit of the processor (Fig. 14, block 1412; [0097]: failure of any one processing unit 14 in the active set 24 is detected in processing apparatus 10 ([0029]: processing apparatus 10 interpreted as a processor));
in response to the first indication, treating the fault as a permanent fault by:
generating, by the controller ([0092]), a first workload allocation scheme to allocate a workload among processing units in which no fault is detected (Fig. 14, step 1414; [0097]: in response to detected failure (block 1412), allocated processing jobs 22 of failed processing unit 14 are redistributed from the failing processing unit 14 to the reserved jobs capacities 32 of the remaining active processing units 14. Fault only detected in the failed processing unit 14, not the remaining active processing units 14 (see [0097]), thus no faults were detected in the remaining active processing units 14 since Fig. 14, blocks 1402-1414); and
instructing, by the controller ([0092]), the processor to process the workload according to the first workload allocation scheme (Fig. 1; Fig. 14; block 1428; [0100]: update data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14);
…generating, by the controller, a revised workload allocation scheme to re-allocate the workload among processing units in which no fault is detected (Fig. 14, steps 1428-1414 loop; [0097]: see first generation limitation above; process loops from step 1428 and distributes (again) allocated processing jobs 22 of the failed processing unit 14 to reserved jobs capacities 32 of the remaining active processing units 14 upon another failure. Also includes activating inactive processing unit 14 to regain desired level of processing redundancy for active set 24 ([0041]) during reallocation); and
…instructing, by the controller, the processor to process the workload according to the revised workload allocation scheme (Fig. 14; block 1428-1428 loop; [0100]: see first instructing limitation above; process loops from step 1428 and updates (again) data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14) upon another failure)
Yan does not disclose:subsequently receiving a second indication that the fault is not detected in the processing unit of the processor; and
in response to the second indication, treating the fault as not permanent by: performing the second “generating” and “instructing” steps
However, Duron teaches:
subsequently receiving a second indication that the fault is not detected in the processing unit of the processor (Fig. 4, step 440; [0034]: the hypervisor 310 determines if the uncorrectable error (UE) is in a processor memory array such as a cache memory of the processor core issuing the core checkstop… Service processor 165 performs a test to determine if the bit steering attempt to correct the error in the offending processor memory array succeeded, as per block 440. If bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1, as per block 445. Service processor 165 receives a second indication (successful bit steering; separate from UE indication from step 420) that the UE is not detected in core 1 of processor 111); and
in response to the second indication, treating the fault as not permanent by:
generating, by the controller, a revised workload allocation scheme to re-allocate the workload among processing units in which no fault is detected ([0028]: when [a] core checkstop occurs, hypervisor 310 moves the workload from that processor core to a spare processor core… the system may transfer that core’s workload and saved checkpoints to another processor core for handling… [the core with the checkstop is removed from] the current configuration of processor cores available to handle data processing activities such as software application execution. Fig. 4, steps 440-455; [0034]: if bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1… the hypervisor 310 reintegrates core C1 of processor 111 into the current configuration when system 105 needs this core 1 for data processing activities. For example, the hypervisor 310 places core C1 of processor 111 into a partition with other processor cores in preparation for data processing activities. Hypervisor 310 generates a revised workload allocation scheme to redistribute data processing activities among the corrected core and other processor cores in which no UE is detected); and
instructing, by the controller, the processor to process the workload according to the revised workload allocation scheme (Fig. 4, step 450; [0034]: the service processor 165 notifies the hypervisor 310 of the new resource, namely that core 1 of processor 111 is in a partition ready for use as a system resource at run time… This error handling process then ends at end block 455. In actual practice, the system 105 continues operating at run time with hypervisor 310 monitoring for local checkstops, as per block 410. Fig. 4, step 420-425; [0033]: loops back to steps 410-420-425, where checkstop of a core (e.g., C1 of processor 111) during runtime is detected and migrates the workload from the detected core to another available core. Thus, processor 111 executes the revised workload (reintegrates C1 with other cores for data processing activities) from steps 445-450 and monitors the revised workload for subsequent runtime checkstop)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan and Duron by implementing UE correction and core reintegration as taught by Duron. One of ordinary skill in the art would be motivated to make this modification in order to reuse the repaired core as a new resource when system 105 needs said core for data processing activities (Duron: [0034]).
Regarding Claim 6, Yan in view of Duron teaches the method of claim 1, as referenced above, further comprising detecting a fault in a processing unit of the processor (Yan: Fig. 14, block 1412; [0097]: failure of any one processing unit 14 in the active set 24 is detected in processing apparatus 10 ([0029]: processing apparatus 10 interpreted as a processor)).
Regarding Claim 7, Yan in view of Duron teaches the method of claim 1, as referenced above, wherein generating the first workload allocation scheme to allocate a workload among processing units in which no fault is detected comprises:
evaluating a processing capacity of the processing units in which no fault is detected (Yan: [0040]: given M = 3 active processing units, each active processing unit 14 has a third of its total jobs capacity 34 reserved in case the other active processing unit fails. The other two active processing units 14 are not regarded as failing);
evaluating a processing requirement of the workload (Yan: [0041]: processing requirement of new processing jobs 22 is effectively evaluated when determining whether more jobs capacity is needed to reallocate processing jobs 22 from a given active processing unit 14 to remaining ones in case of failure of that given unit 14);
determining whether the processing capacity is greater than the processing requirement (Yan: [0041]: reserved jobs capacity 32 is effectively determined to be greater than or less than the processing requirement of processing jobs 22 in order to determine whether one or more inactive processing units 14 should be activated to provide sufficient processing capacity equal to the total jobs capacity of a single processing unit 14 for jobs 22); and
in response to determining that the processing capacity is greater than the processing requirement, generating the first workload allocation scheme to allocate an entirety of the workload among the processing units in which no fault is detected; or
in response to determining that the processing capacity is not greater than the processing requirement, generating the first workload allocation scheme to allocate a portion of the workload among the processing units in which no fault is detected (Yan: [0041]: if more jobs capacity is needed to preserve the defined level of processing capacity ([0093]: M = defined level of processing redundancy = provides processing resources sufficient for allocation of processing load 20; [0031]: processing load 20 comprises of individually allocable jobs 22), one or more inactive processing units 14 is activated. Jobs 22 is then re-allocated from the failed processing unit 14 to remaining ones (i.e., a portion of load 20 towards M – 1 previously active processing units, and another portion towards the newly activated processing unit(s)).
Regarding Claim 12, Yan in view of Duron teaches the method of claim 1, as referenced above, wherein instructing the processor to process the workload according to the first workload allocation scheme or the revised workload allocation scheme comprises writing the respective workload allocation scheme to storage (Yan: Fig. 14, block 1428; [0100]: update data record 19 – e.g., changes in the mapping of processing jobs 22 to particular processing units 14).
Regarding Claim 13, Yan in view of Duron teaches the method of claim 1, as referenced above, wherein a maximum utilization of the processor required to process the workload is less than a predetermined threshold utilization to overprovision the processor with processing capacity by at least a processing capacity of one processing unit (Yan: [0040]: 1/M of the total jobs capacity 30 of each remaining active processing unit 14 is reserved to re-allocate jobs of a failing active processing unit 14. The other ((M-1) / M) of the total jobs capacity 30 is dedicated to normal allocation usage. Therefore, a maximum utilization from the reserved jobs capacity 32 (denoted as 1/M of total jobs capacity 30) is less than a threshold utilization of 100% to overprovision the processor with jobs capacity in the event of a failed processing unit 14. The processing card is overprovisioned by the reserved capacity 32 of the remaining active processing units 14).
Regarding Claim 14, Yan discloses a processor comprising a plurality of processing units and controller circuitry (Fig. 1: processing apparatus 10, processing units 14-1…140N, control circuit) configured to:
receive, from fault detection circuitry ([0092]: control circuit 18; serves as controller + fault detection circuitry), a first indication that a fault is detected in a processing unit of the processor (Fig. 14, block 1412; [0097]: failure of any one processing unit 14 in the active set 24 is detected in processing apparatus 10 ([0029]: processing apparatus 10 interpreted as a processor));
in response to the first indication, treat the fault as a permanent fault by:
generating, at the controller circuitry ([0092]), a first workload allocation scheme to allocate a workload among processing units in which no fault is detected (Fig. 14, step 1414; [0097]: in response to detected failure (block 1412), allocated processing jobs 22 of failed processing unit 14 are redistributed from the failing processing unit 14 to the reserved jobs capacities 32 of the remaining active processing units 14. Fault only detected in the failed processing unit 14, not the remaining active processing units 14 (see [0097]), thus no faults were detected in the remaining active processing units 14 since Fig. 14, blocks 1402-1414); and
instructing the processing units to process the workload according to the first workload allocation scheme (Fig. 1; Fig. 14; block 1428; [0100]: update data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14);
…generating, at the controller circuitry, a revised workload allocation scheme to re- allocate the workload among processing units in which no fault is detected (Fig. 14, steps 1428-1414 loop; [0097]: see first generation limitation above; process loops from step 1428 and distributes (again) allocated processing jobs 22 of the failed processing unit 14 to reserved jobs capacities 32 of the remaining active processing units 14 upon another failure. Also includes activating inactive processing unit 14 to regain desired level of processing redundancy for active set 24 ([0041]) during reallocation); and
…instructing the processor to process the workload according to the revised workload allocation scheme (Fig. 14; block 1428-1428 loop; [0100]: see first instructing limitation above; process loops from step 1428 and updates (again) data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14) upon another failure)
Yan does not disclose:
subsequently receive a second indication that the fault is not detected in the processing unit of the processor; and
in response to the second indication, treat the fault as not permanent by: performing the second “generating” and second “instructing” steps
However, Duron teaches:
subsequently receive a second indication that the fault is not detected in the processing unit of the processor (Fig. 4, step 440; [0034]: the hypervisor 310 determines if the uncorrectable error (UE) is in a processor memory array such as a cache memory of the processor core issuing the core checkstop… Service processor 165 performs a test to determine if the bit steering attempt to correct the error in the offending processor memory array succeeded, as per block 440. If bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1, as per block 445. Service processor 165 receives a second indication (successful bit steering; separate from UE indication from step 420) that the UE is not detected in core 1 of processor 111); and
in response to the second indication, treat the fault as not permanent by:
generating, at the controller circuitry, a revised workload allocation scheme to re- allocate the workload among processing units in which no fault is detected ([0028]: when [a] core checkstop occurs, hypervisor 310 moves the workload from that processor core to a spare processor core… the system may transfer that core’s workload and saved checkpoints to another processor core for handling… [the core with the checkstop is removed from] the current configuration of processor cores available to handle data processing activities such as software application execution. Fig. 4, steps 440-455; [0034]: if bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1… the hypervisor 310 reintegrates core C1 of processor 111 into the current configuration when system 105 needs this core 1 for data processing activities. For example, the hypervisor 310 places core C1 of processor 111 into a partition with other processor cores in preparation for data processing activities. Hypervisor 310 generates a revised workload allocation scheme to redistribute data processing activities among the corrected core and other processor cores in which no UE is detected); and
instructing the processor to process the workload according to the revised workload allocation scheme (Fig. 4, step 450; [0034]: the service processor 165 notifies the hypervisor 310 of the new resource, namely that core 1 of processor 111 is in a partition ready for use as a system resource at run time… This error handling process then ends at end block 455. In actual practice, the system 105 continues operating at run time with hypervisor 310 monitoring for local checkstops, as per block 410. Fig. 4, step 420-425; [0033]: loops back to steps 410-420-425, where checkstop of a core (e.g., C1 of processor 111) during runtime is detected and migrates the workload from the detected core to another available core. Thus, processor 111 executes the revised workload (reintegrates C1 with other cores for data processing activities) from steps 445-450 and monitors the revised workload for subsequent runtime checkstop)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan and Duron by implementing UE correction and core reintegration as taught by Duron. One of ordinary skill in the art would be motivated to make this modification in order to reuse the repaired core as a new resource when system 105 needs said core for data processing activities (Duron: [0034]).
Regarding Claim 16. Yan in view of Duron teaches the processor of claim 14, as referenced above, wherein the controller circuitry is further configured to:
evaluate a processing requirement of the workload (Yan: [0041]: processing requirement of new processing jobs 22 is effectively evaluated when determining whether more jobs capacity is needed to reallocate processing jobs 22 from a given active processing unit 14 to remaining ones in case of failure of that given unit 14);
determine whether a processing capacity of the processing units in which no fault is detected is greater than the processing requirement (Yan: [0041]: reserved jobs capacity 32 is effectively determined to be greater than or less than the processing requirement of processing jobs 22 in order to determine whether one or more inactive processing units 14 should be activated to provide sufficient processing capacity equal to the total jobs capacity of a single processing unit 14 for jobs 22); and
in response to determining that the processing capacity of the processing units in which no fault is detected is greater than the processing requirement, generate, at the controller circuitry, the first workload allocation scheme to allocate an entirety of the workload among the processing units in which no permanent fault is detected;
or in response to determining that the processing capacity of the processing units in which no fault is detected is not greater than the processing requirement, generate, at the controller circuitry, the first workload allocation scheme to allocate a portion of the workload among the processing units in which no fault is detected (Yan: [0041]: if more jobs capacity is needed to preserve the defined level of processing capacity ([0093]: M = defined level of processing redundancy = provides processing resources sufficient for allocation of processing load 20; [0031]: processing load 20 comprises of individually allocable jobs 22), one or more inactive processing units 14 is activated. Jobs 22 is then re-allocated from the failed processing unit 14 to remaining ones (i.e., M – 1 previously active processing units, and the newly activated processing unit(s)).
Claims 2 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Duron, in further view of Inoue et al. (US 20100162042 A1, as previously cited, hereinafter “Inoue”)
Regarding Claim 2, Yan in view of Duron teaches the method of claim 1, as referenced above.
Yan in view of Duron does not teach:
wherein the processor comprises a safety critical processor comprising a plurality of safety critical processing units.
However, Inoue teaches:
wherein the processor comprises a safety critical processor comprising a plurality of safety critical processing units (Fig. 1; [0036]; [0041]: each of the processor cores 0, 1, 2, and 3 executes programs such as the OS and an application which is operated on the OS for realizing the vehicle control and the information control… As specific examples of the OS to be processed by the processor cores 0, 1, 2, and 3, there [is] a real time OS (RT_OS) as the OS for the vehicle control. [0042]: In the application program for the vehicle control, a predetermined process must be executed in real time so that high responsiveness and high safety are secured. Therefore, it is preferable that the RT-OS be used for the vehicle control since the RT-OS can process the program in real time. Multicore processor 10 includes cores 0, 1, 2, and 3 for executing high responsive and high safety vehicle control).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to perform a simple substitution of one known element (Yan: Fig. 1: generic processing units 14-1 to 14-N) for another (Inoue: multicore processor with cores that execute high responsive and high safety vehicle control) to obtain predictable results (a processor with a plurality of processing units).
Regarding Claim 8, Yan in view of Duron teaches the method of claim 7, as referenced above, wherein generating the first workload allocation scheme to allocate a portion of the workload among the processing units in which no fault is detected comprises:
evaluating a processing requirement of the workload (Yan: [0041]: processing requirement of new processing jobs 22 is effectively evaluated when determining whether more jobs capacity is needed to reallocate processing jobs 22 from a given active processing unit 14 to remaining ones in case of failure of that given unit 14);
determining whether the processing capacity is greater than the processing requirement of the workload (Yan: [0041]: reserved jobs capacity 32 is effectively determined to be greater than or less than the processing requirement of processing jobs 22 in order to determine whether one or more inactive processing units 14 should be activated to provide sufficient processing capacity equal to the total jobs capacity of a single processing unit 14 for jobs 22);
in response to determining that the processing capacity is greater than the processing requirement of the workload, generating the first workload allocation scheme to allocate an entirety of the workload among the processing units in which no fault is detected (Yan: [0041]: allocates new processing jobs 22 to remaining active processing units 14 until more jobs capacity is needed to preserve the predefined level of processing redundancy. [0061]: increases the processing capacity (M) when the count of current processing jobs 22 in processing load 20 equals count of slots 44 included in the aggregate allocable jobs capacity 42. Therefore, in response to determining that the count of slots 44 in aggregate allocable jobs capacity 42 is greater than the count of processing jobs 22, M is not increased and the entirety of jobs 22 is allocated to the remaining processing units 14 without activating additional processing units).
Yan in view of Duron does not teach:
identifying a high priority portion of the workload;
However, Inoue teaches:
identifying a high priority portion of the workload and generating a workload allocation scheme based on the high priority portion of the workload ([0049]: when an abnormal operation occurs in core 0 to which the vehicle control (the highest priority control) is allocated, the monitoring processor 20 instructs a change such that the process by ALP 0a for vehicle control being executed by processor 0 is continued by core 1);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to perform a simple substitution of one known element (Yan: [0041]: generic processing jobs 22 as the failed workload) for another (INOUE: [0049]: high priority jobs as the failed workload) to obtain predictable results (reallocating jobs of a failed workload).
Regarding Claim 9, Yan in view of Duron, in further view of Inoue teaches the method of claim 8, as referenced above, wherein the high priority portion of the workload is a safety critical portion of the workload (Inoue: [0049]: vehicle control is the highest priority control. [0039]: vehicle control is responsible for driving functions, turning functions, stopping functions, engine control, steering wheel control, braking control, and supporting control. These various functions and controls encompass safety critical workload for operating the vehicle).
Claims 3, 5, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Duron, in further view of Swanson et al. (US 20140164827 A1, as previously cited, hereinafter “Swanson”).
Regarding Claim 3, Yan in view of Duron teaches the method of claim 1, as referenced above, wherein receiving the first indication that a fault is detected in a processing unit of the processor comprises:
receiving an indication that a fault is detected (Yan: Fig. 14, block 1412; [0097]: failure of any one processing unit 14 in the active set 24 is detected in processing apparatus 10 ([0029]: processing apparatus 10 interpreted as a processor)); and
Yan in view of Duron does not teach:
receiving an indication of a location within the processor of the fault.
However, Swanson teaches:
receiving an indication of a location within the processor of the fault ([0038]: during processor core swap in response to reaching the error threshold, firmware 224 selects the processor core(s) of the spare set 204 to use as replacement core(s) based on the die location of the failed or failing processor core 104).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan, Duron, and Swanson by implementing the die location taught by Swanson. One of ordinary skill in the art would be motivated to make this modification in order to minimize future errors and latency when replacing the failed core with another core (Swanson: [0017]).
Regarding Claim 5, Yan in view of Duron teaches the method of claim 1, as referenced above.
Yan in view of Duron does not teach:
wherein receiving the first indication that a fault is detected in a processing unit of the processor comprises retrieving the first indication from storage.
However, Swanson teaches:
wherein receiving the first indication that a fault is detected in a processing unit of the processor comprises retrieving the first indication from storage ([0037]: firmware 224 updates an error tracking counter associated with the processor core 104 responsible for the processor core error. The error tracking counter may be embodied as any type of software counter or register for tracking the number of occurrences of processor core errors by the respective processor core 104. In block 522, the firmware 224 determines whether the error tracking counter for the associated processing core 104 has reached a reference threshold value (e.g., has the respective processor core 104 generated a number of processor core errors equal to or greater than the reference threshold value)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan, Duron, and Swanson by implementing the error counter taught by Swanson. One of ordinary skill in the art would be motivated to make this modification in order to determine when a number of errors may be encountered before requiring a full workload migration to another core ([0037]-[0039]).
Regarding Claim 17, Yan in view of Duron teaches the processor of claim 14, as referenced above.
Yan in view of Duron does not teach:
wherein the processing units are arranged to operate in a parallel processing arrangement.
However, Swanson teaches:
wherein the processing units are arranged to operate in a parallel processing arrangement (Fig. 1 and [0016]: processors 102 includes one or more processor cores 104 such that, in some embodiments, computing device 100 may include fifty or more cores. [0001]: high-performance computing systems may utilize fifty or more cores to perform various workloads, wherein the cores may be small cores designed for highly parallel computing).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to further combine Yan, Duron, and Swanson by performing a simple substitution of one known element (Yan: Fig. 1: generic processing units) for another (Swanson: [0016]: small cores) to obtain predictable results (plurality of processing units).
Regarding Claim 18, Yan discloses a host processor configured to execute a driver to allocate a workload among processing units of a subject processor (Fig. 1: host and subject processing apparatus 10. Fig. 14; [0092]: execute control circuit 18 to allocate jobs 22 among active processing units 14 in method 1400), the driver being configured to:
retrieve… a first indication that a fault is detected in a processing unit of the subject processor (Fig. 14, block 1412; [0097]: detect failure of any one processing unit 14 of processing apparatus 10);
in response to the first indication, treat the fault as a permanent fault by:
generating a first a workload allocation scheme, wherein the first workload allocation scheme is implementable by the subject processor to allocate a workload among processing units of the subject processor in which no fault is detected (Fig. 14, step 1414; [0097]: in response to detected failure (block 1412), allocated processing jobs 22 of failed processing unit 14 are redistributed from the failing processing unit 14 to the reserved jobs capacities 32 of the remaining active processing units 14. Fault only detected in the failed processing unit 14, not the remaining active processing units 14 (see [0097]), thus no faults were detected in the remaining active processing units 14 since Fig. 14, blocks 1402-1414); and
writing, to storage, the first workload allocation scheme for implementation by the subject processor to process the workload despite presence of a fault (Fig. 1; Fig. 14; block 1428; [0100]: update data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14);
…generating a revised workload allocation scheme; wherein the revised workload allocation scheme is implementable by the subject processor to re-allocate a workload among processing units of the subject processor in which no fault is detected (Fig. 14, steps 1428-1414 loop; [0097]: see first generation limitation above; process loops from step 1428 and distributes (again) allocated processing jobs 22 of the failed processing unit 14 to reserved jobs capacities 32 of the remaining active processing units 14 upon another failure. Also includes activating inactive processing unit 14 to regain desired level of processing redundancy for active set 24 ([0041]) during reallocation); and
…writing, to storage, the revised workload allocation scheme for implementation by the subject processor to process the workload according to the revised workload allocation scheme (Fig. 14; block 1428-1428 loop; [0100]: see first writing limitation above; process loops from step 1428 and updates (again) data record 19 (shown in Fig. 1 part of processing apparatus 10) to reflect changes in allocation details – e.g., changes in the mapping of processing jobs 22 to particular processing units 14) upon another failure)
Yan does not disclose:
retrieve, from storage…
subsequently retrieve, from storage, a second indication that the fault is not detected in the processing unit of the subject processor; and
in response to the second indication, treat the fault as not permanent by: performing the second “generating” and second “writing” limitations
However, Duron teaches:
subsequently retrieve, from storage, a second indication that the fault is not detected in the processing unit of the subject processor (Fig. 4, step 440; [0034]: the hypervisor 310 determines if the uncorrectable error (UE) is in a processor memory array such as a cache memory of the processor core issuing the core checkstop… Service processor 165 performs a test to determine if the bit steering attempt to correct the error in the offending processor memory array succeeded, as per block 440. If bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1, as per block 445. Service processor 165 receives a second indication (successful bit steering; separate from UE indication from step 420) that the UE is not detected in core 1 of processor 111); and
in response to the second indication, treat the fault as not permanent by:
generating a revised workload allocation scheme; wherein the revised workload allocation scheme is implementable by the subject processor to re-allocate a workload among processing units of the subject processor in which no fault is detected ([0028]: when [a] core checkstop occurs, hypervisor 310 moves the workload from that processor core to a spare processor core… the system may transfer that core’s workload and saved checkpoints to another processor core for handling… [the core with the checkstop is removed from] the current configuration of processor cores available to handle data processing activities such as software application execution. Fig. 4, steps 440-455; [0034]: if bit steering succeeded in correcting the error that was uncorrectable during the offending core 1 run time, then service processor 165 finishes reinitialization of this processor core 1… the hypervisor 310 reintegrates core C1 of processor 111 into the current configuration when system 105 needs this core 1 for data processing activities. For example, the hypervisor 310 places core C1 of processor 111 into a partition with other processor cores in preparation for data processing activities. Hypervisor 310 generates a revised workload allocation scheme to redistribute data processing activities among the corrected core and other processor cores in which no UE is detected); and
writing, to storage, the revised workload allocation scheme for implementation by the subject processor to process the workload according to the revised workload allocation scheme (Fig. 4, step 450; [0034]: regarding command for core reintegration into current configuration and notification to hypervisor 310 that the core is a new resource ready for use as a system resource at runtime).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan and Duron by implementing UE correction and core reintegration as taught by Duron. One of ordinary skill in the art would be motivated to make this modification in order to reuse the repaired core as a new resource when system 105 needs said core for data processing activities (Duron: [0034]).
Yan in view of Duron does not teach:
retrieve, from storage…
However, Swanson teaches:
retrieve, from storage, a first indication that a fault is detected in a processing unit of the subject processor (Fig. 5, block 522 and [0037]: firmware 224 retrieves an indication (via error tracking counter, embodied as a software counter or register) that the respective processor core 104 (Fig. 1: of processor 102) has reached a reference threshold value of processor core errors);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan, Duron, and Swanson by implementing the error counter taught by Swanson. One of ordinary skill in the art would be motivated to make this modification in order to determine when a number of errors may be encountered before requiring a full workload migration to another core ([0037]-[0039]).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Duron, in further view of Swanson, in further view of DE PAULA ROSA PIGA et al. (US 20210406092 A1, as previously cited, hereinafter “DE PAULA ROSA PIGA”).
Regarding Claim 4, Yan in view of Duron, in further view of Swanson teaches the method of claim 3, as referenced above, wherein the indication of the location within the processor comprises… an identifier ((Swanson: Fig. 5, block 524 and [0038]: firmware 224 selects the processor core(s) of the replacement spare set 204 to use as replacement core(s) based on the die location. Firmware 224 updates the main processor core description table 212 to add the replacement core 104 from spare set 204 and remove the replacement core 104 from spare processor core description table 214. [0016]: each description table identifies each processor core 104 of the main set 202 and spare set 204, respectively. Therefore, die location also includes a core identifier to update the main and spare tables accordingly).
Yan in view of Duron, in further view of Swanson does not teach:
one or more selected from the list: partition identifier; shader slice identifier; cache identifier, shader core identifier.
However, DE PAULA ROSA PIGA teaches:
one or more selected from the list: partition identifier; shader slice identifier; cache identifier, shader core identifier ([0024]: communicates an identifier 112 of the selected core 110 to run each workload. [0020]: processing cores 110 are referred to as shader cores).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to perform a simple substitution of one known element (Swanson: generic core ID based on die location) for another (DE PAULA ROSA PIGA: shader core ID) to obtain predictable results (core ID).
Regarding Claim 15, Yan in view of Duron teaches the processor of claim 14, as referenced above.
Yan in view of Duron does not teach:
wherein the first indication that a fault is detected in a processing unit of the processor comprises one or more indications of a location for the fault selected from the list: partition identifier; shader slice identifier; shader core identifier.
However, Swanson teaches:
wherein the first indication that a fault is detected in a processing unit of the processor comprises one or more indications of a location for the fault (Fig. 5, block 524 and [0038]: firmware 224 selects the processor core(s) of the replacement spare set 204 to use as replacement core(s) based on the die location. Firmware 224 updates the main processor core description table 212 to add the replacement core 104 from spare set 204 and remove the replacement core 104 from spare processor core description table 214. [0016]: each description table identifies each processor core 104 of the main set 202 and spare set 204, respectively. Therefore, die location also includes a core identifier to update the main and spare tables accordingly)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan, Duron, and Swanson by implementing the die location taught by Swanson. One of ordinary skill in the art would be motivated to make this modification in order to minimize future errors and latency when replacing the failed core with another core (Swanson: [0017]).
Yan in view of Duron, in further view of Swanson does not teach:
… selected from the list: partition identifier; shader slice identifier; shader core identifier.
However, DE PAULA ROSA PIGA teaches:
….selected from the list: partition identifier; shader slice identifier; cache identifier, shader core identifier ([0024]: communicates an identifier 112 of the selected core 110 to run each workload. [0020]: processing cores 110 are referred to as shader cores).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to perform a simple substitution of one known element (Swanson: generic core ID based on die location) for another (DE PAULA ROSA PIGA: shader core ID) to obtain predictable results (core ID).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Duron, in further view of Inoue, in further view of SUN (EP 3799390 A1, as previously cited), and in further view of Aronovich et al. (US 20230125765 A1, as previously cited, hereinafter “Aronovich”).
Regarding Claim 10, Yan in view of Duron, in further view of Inoue teaches the method of claim 8, as referenced above, wherein identifying a high priority portion of the workload comprises:
determining a job criticality indicator for each job of the workload (Inoue: [0037]: control (job) criticality is determined when allocated to each processor core 0-3, wherein each core 0-3 has a priority order);
evaluating a processing requirement for each job of the workload (Yan: [0041]: processing requirement of new processing jobs 22 is effectively evaluated when determining whether more jobs capacity is needed to reallocate processing jobs 22 from a given active processing unit 14 to remaining ones in case of failure of that given unit 14); and
Yan in view of Duron, in further view of Inoue does not teach:
excluding from the workload jobs having a job criticality indicator below a predetermined threshold criticality in descending order of processing requirement until the processing requirement of the workload falls below the processing capacity, or until no jobs having a job criticality indicator below the predetermined threshold criticality remain.
However, SUN teaches:
excluding from the workload jobs having a job criticality indicator below a predetermined threshold criticality until the processing requirement of the workload falls below the processing capacity ([0009]: removes a task having a priority lower than a priority of the target task until the remaining resources obtained after the physical node executes remaining tasks satisfy the resources required for running the target task), or until no jobs having a job criticality indicator below the predetermined threshold criticality remain.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Swanson, Yan, Inoue, and SUN by implementing the task removal scheme taught by SUN. One of ordinary skill in the art would be motivated to make this modification in order to provide sufficient resources required for running the prioritized, target task (SUN: [0009]).
Yan in view of Duron, in view of Inoue, in further view of SUN does not teach:
…in descending order of processing requirement…
However, Aronovich teaches:
excluding from the workload jobs… in descending order of processing requirement ([0170]: a ratio of job priorities to resource requirement size is generated for each container pool and are sorted into ascending order. As job priorities are lower and as resource requirements are higher, a lower benefit to cost ratio is present. A container pool is placed higher in the ranking, indicating that the container pool is a more desirable candidate for removing. [0171]: process removes idle containers using the order from sorting the container pools without exceeding the maximum number of containers that can be removed and until sufficient resources are available. Therefore, containers (which contain jobs) are excluded in descending order of benefit (jobs priority) : cost (resource requirement) until the max removal threshold is reached or sufficient resources are available).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Swanson, Yan, Inoue, SUN, and Aronovich by implementing removal scheme taught by Aronovich. One of ordinary skill in the art would be motivated to make this modification in order to optimize benefit : cost in terms of job priority and resource requirement (Aronovich: [0170]).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Duron, in view of Swanson, in further view of KUMAR et al. (US 20220158921 A1, hereinafter “KUMAR”).
Regarding Claim 19. Yan in view of Duron, in view of Swanson teaches the host processor of claim 18, as referenced above, wherein the driver is further configured to:
generate the first workload allocation scheme in response to the first indication
Yan in view of Duron, in view of Swanson does not teach:
retrieve, from storage, utilization data for the subject processor; and
generate the first workload allocation scheme in response the utilization data.
However, KUMAR teaches:
retrieve, from storage, utilization data for the subject processor ([0035]: traffic controller determines current utilization of CPU 1 and determines potential utilization and potential PPS based on the current utilization. [0031]: current CPU utilization is based on current throughput rate of tunnel traffic, which is measured by a counter ([0029]: value of counter is understood to be stored in memory)); and
generate the first workload allocation scheme in response the utilization data ([0036]: selects a CPU of the plurality of CPUs to associate with the new tunnel traffic based on potential PPS limit associated with the CPU).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Yan, Duron, Swanson, and KUMAR by implementing the CPU utilization-based traffic allocation scheme taught by KUMAR as taught by KUMAR. One of ordinary skill in the art would be motivated to make this modification in order to optimize task processing using a faster, more efficient processing unit (KUMAR: [0013]).
Regarding Claim 20, Yan in view of Duron, in view of Swanson, in further view of KUMAR teaches the host processor of claim 19, as referenced above, wherein the utilization data comprises at least one of:
a predetermined threshold utilization;
an identity of a processing unit operating at a utilization below the predetermined threshold utilization;
a difference between the utilization of the processing unit and the predetermined threshold utilization (KUMAR: [0035]: utilization data comprises a difference between current utilization and a maximum threshold of 100% utilization to compute potential utilization of CPU 1 and potential PPS).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The elements of Claim 11 were neither found through a search of prior art nor considered obvious by the Examiner. In particular, the prior art of record does not teach nor suggest, in combination with the remaining limitations and in the context of their claims as a whole:
“…determining a job degradability indicator for each job having a job criticality indicator below the predetermined threshold criticality; evaluating a processing requirement for a degraded execution of each job of the workload having a job degradability indicator above a predetermined threshold degradability; evaluating a processing requirement for non-degraded execution of each job of the workload having a job degradability indicator below the predetermined threshold degradability…”
See Office Action mailed on 11/13/2025, Section “Allowable Subject Matter” for closest prior art and analysis.
Response to Arguments
Applicant's arguments, filed 05/14/2026, regarding 35 U.S.C. 103 have been fully considered but are moot.
Applicant’s arguments, see Pages 9-12, with respect to 35 U.S.C. 101 have been fully considered and are persuasive. The rejections of claims 1-20 has been withdrawn.
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly cited art Duron teaches the amended limitations of claim 1 and similar independent claims. Please see above for more detail.
Conclusion
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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