DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending. Claims 1, 11, and 13 are independent.
Information Disclosure Statement
Applicant’s Information Disclosure Statements (IDSs) filed October 29, 2024, and
July 2, 2026, have been considered.
Claim Objections
Claims 5 and 16-19 are objected to because of the following typographical informalities:
Regarding claim 5, in the last clause, replace “store an initial sensing result the cache storage unit” with—store an initial sensing result into the cache storage unit—.
Regarding claim 16, in the second clause, replace “performing the read operation on the second memory cell is further comprises” with—performing the read operation on the second memory cell further comprises—.
Regarding claim 17, in the second clause, replace “performing the read operation on the second memory cell is further comprises” with—performing the read operation on the second memory cell further comprises—.
Regarding claim 18, in the second clause, replace “performing the read operation on the second memory cell is further comprises” with—performing the read operation on the second memory cell further comprises—.
Regarding claim 19, in the second clause, replace “performing the read operation on the second memory cell is further comprises” with—performing the read operation on the second memory cell further comprises—.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 and 5-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 8, and 10-12, 14, 18-20 of U.S. Patent No. 12,159,676-B2.
Independent Claim 1 is met by U.S. Patent 12159676 claims 1-3, which directly store into the cache storage unit data sensed from the second memory cell because at least “first page data stored in the second memory cell” (claim 2) is “sens[ed]” (claim 2) and “set . . . in the cache storage unit” (claim 3) without any intervening elements.
Claims 2 and 3 are met by U.S. Patent 12159676 claim 10.
Claims 5-8 are met by U.S. Patent 12159676 claims 3 & 4, as well as claims 5, 6, and 7.
Claim 9 is met by U.S. Patent 12159676 claim 10.
Claim 10 is met by U.S. Patent 12159676 claim 8.
Independent Claim 11 is met by U.S. Patent 12159676 claims 11-13, which directly store into the cache storage unit data sensed from the second memory cell because at least “first page date stored in the second memory cell” (claim 12) is “sens[ed]” (claim 12) and “set . . . in the cache storage unit” (claim 13) without any intervening elements.
Claim 12 would have been obvious considering U.S. Patent 12159676 claims 1 and 10, in the context of a “memory system” as recited in U.S. Patent 12159676 claim 11.
Independent Claim 13 is met by U.S. Patent 12159676 claims 18-20, which directly store into the cache storage unit data sensed from the second memory cell because at least “first page date stored in the second memory cell” (claim 19) is “sens[ed]” (claim 19) and “set . . . in the cache storage unit” (claim 20) without any intervening elements. Additionally, Claim 13 would have been an obvious method of operation over U.S. Patent 12159676 Claims 1-3 memory device. Claims 14-20 would have been obvious methods of operation over U.S. Patent 12159676 Claims 1-8 and 10 memory device for the reasons above with respect to application claims 1-3 and 4-9, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6, 9-11, 13, 16, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hosono et al. (US 20030169630 A1).
Regarding independent claim 1, Hosono teaches a memory device, comprising:
an array of memory cells (FIG. 1: memory cell array 100) comprising
a first memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC0)
and a second memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC1),
wherein each of the first memory cell and the second memory cell is configured to store N-bits data (FIG. 6: memory cell MC; see para. 58: “This memory cell MC stores a bit data”; see also para. 89);
and a peripheral circuit (FIG. 1: (e.g.) logic control circuit 220, controller 110, and read/write circuit (page buffer) 200) coupled to the array of memory cells (FIG. 1: read/write circuit (page buffer) 200 coupled to memory cell array 100) and comprising:
a page buffer (FIG. 1: read/write circuit (page buffer) 200) comprising
at least a page buffer circuit (FIG. 3: page buffer 200, first page buffer circuit 200a, and second page buffer circuit 200b) that is coupled to the first and second memory cells (FIG. 3: page buffer circuits 200a and 200b coupled to bit lines BL0-BLn-1), respectively,
the page buffer circuit comprising a sense out (SO) node (FIG. 3: output from pre-sense circuit Pre SA 31) and a cache storage unit (FIG. 3: second page buffer circuit 200b; see also para. 52: “200b is for use as a cache which temporarily holds write/read data therein”);
and control logic coupled to the page buffer (FIG. 1: logic control circuit 220 and controller 110 coupled to page buffer 200) and configured to:
suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell (see para. 90: “write operation is suspended; then, reading of…Row2…carried out while holding the write data in the first page buffer 200a”; see also FIG. 10A-H and e.g. FIG. 11);
control the page buffer circuit to store suspended program information associated with a suspension of the program operation (see para. 90: “write operation is suspended; then, reading of…Row2…carried out while holding the write data in the first page buffer 200a”; see also FIG. 10A-H and e.g. FIG. 11); and
perform the read operation on the second memory cell, comprising directly storing (see para. 90: “directly read out to nodes N21 of the second page buffer 200b”) one of N-bits data of the second memory cell (see e.g. FIG. 10E: <Read from Row2 cells>) into the cache storage unit (FIG. 3: second page buffer circuit 200b) through the SO node (FIG. 3: output from pre-sense circuit Pre SA 31; see also para. 90: “cell data are directly read out to the nodes N21 of the second page buffer 200b).
Regarding claim 4, Hosono teaches the memory device of claim 1 (see prior paragraph regarding claim 1),
wherein a number of latches in the page buffer circuit is N+2 (FIG. 3: first page buffer latch circuits 32, second page buffer latch circuits 36; see also para. 44: “data read/write circuit 200 includes…latch circuits (DL), which are provided in units of bit lines in order to perform data reading and writing (programming) operations in a parallel fashion with respect to a plurality of cells at a certain address of the memory cell array 100”).
Regarding claim 5, Hosono teaches the memory device of claim 1 (see prior paragraph regarding claim 1),
wherein to perform the read operation on the second memory cell (FIG. 1: memory cells of memory cell array 100),
the control logic (FIG. 1: logic control circuit 220) is further configured to:
precharge (e.g. FIG. 4: first page buffer 200a, transistor 42; see also para. 55: “A precharge-use NMOS transistor 42 is provided at the sense node N0”) the SO node (FIG. 3: page buffer 200, output from pre-sense circuit Pre SA 31; see also FIG. 4: first page buffer 200a, node N0);
and store an initial sensing result [in] the cache storage unit (see e.g. FIG. 11: operation at time t30-t32; see also FIG. 10A: <Read from Row1 cells>).
Figure 4 diagrams the configuration of the first page buffer 200a of Figure 3. Figure 3 shows that the first page buffer 200a and the second page buffer 200b are identical. Thus, when data is to be read out and stored in page buffer 200b during a copy write operation, the precharge-use transistor(s) of first page buffer 200a being also found in page buffer 200b meets the limitation of precharging of the SO node(s) of the relevant page buffer circuit during the reading operation as evident by the structural pre-charging capabilities of the page buffer circuits 200a and 200b.
Regarding claim 6, Hosono teaches the memory device of claim 5 (see prior paragraph regarding claim 5),
wherein to perform the read operation on the second memory cell (see para. 90: “write operation is suspended; then, reading of…Row2…carried out”; see also FIG. 10A-H and e.g. FIG. 11), the control logic is further configured to:
apply a first sensing level to the second memory cell; and store a first sensing result into the cache storage unit (FIG. 3: second page buffer circuit 200b) through the SO node (FIG. 3: output from pre-sense circuit Pre SA 31; see also para. 90: “cell data are directly read out to the nodes N21 of the second page buffer 200b).
Regarding claim 9, Hosono teaches the memory device of claim 1 (see prior paragraph regarding claim 1),
wherein the control logic (FIG. 1: logic control circuit 220) is further configured to
sense each of the N-bits data of the second memory cell one by one through the SO node and the cache storage unit node (FIG. 3: page buffer 200, output from pre-sense circuit Pre SA 31; see also FIG. 4: first page buffer 200a, node N0).
Regarding claim 10, Hosono teaches the memory device of claim 1 (see prior paragraph regarding claim 1),
wherein the control logic (FIG. 1: logic control circuit 220) is further configured to:
responsive to a completion of the read operation, control the page buffer circuit (FIG. 3: page buffer 200) to resume the program operation on the first memory cell using the suspended program information (see e.g. FIG. 11: programming operation at time t33-t36, interrupting read operation and suspension of programming operation at time t37-39, resuming programming operation at time t39; see also FIG. 10A-H).
Regarding independent claim 11, Hosono teaches a memory system, comprising:
a memory device (see para. 3: “This invention relates…to an electrically rewritable non-volatile semiconductor memory device) comprising:
an array of memory cells (FIG. 1: memory cell array 100) comprising
a first memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC0) and a second memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC1),
wherein each of the first memory cell and the second memory cell is configured to store N-bits data (FIG. 6: memory cell MC; see para. 58: “This memory cell MC stores a bit data”; see also para. 89);
and a peripheral circuit (FIG. 1: (e.g.) logic control circuit 220, controller 110, and read/write circuit (page buffer) 200)
coupled to the array of memory cells (FIG. 1: read/write circuit (page buffer) 200 coupled to memory cell array 100) and comprising:
a page buffer (FIG. 1: read/write circuit (page buffer) 200) comprising at least
a page buffer circuit (FIG. 3: page buffer 200, first page buffer circuit 200a, and second page buffer circuit 200b)
that is coupled to the first and second memory cells (FIG. 3: page buffer circuits 200a and 200b coupled to bit lines BL0-BLn-1), respectively,
the page buffer circuit comprising a sense out (SO) node (FIG. 3: output from pre-sense circuit Pre SA 31) and a cache storage unit (FIG. 3: second page buffer circuit 200b; see also para. 52: “200b is for use as a cache which temporarily holds write/read data therein”);
and control logic coupled to the page buffer (FIG. 1: logic control circuit 220 and controller 110 coupled to page buffer 200) and configured to:
suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell (see para. 90: “write operation is suspended; then, reading of…Row2…carried out while holding the write data in the first page buffer 200a”; see also FIG. 10A-H and e.g. FIG. 11);
control the page buffer circuit to store suspended program information associated with a suspension of the program operation (see para. 90: “write operation is suspended; then, reading of…Row2…carried out while holding the write data in the first page buffer 200a”; see also FIG. 10A-H and e.g. FIG. 11); and
perform the read operation on the second memory cell, comprising directly storing one of N-bits data of the second memory cell (see e.g. FIG. 10E: <Read from Row2 cells>) into the cache storage unit (FIG. 3: second page buffer circuit 200b) through the SO node (FIG. 3: output from pre-sense circuit Pre SA 31; see also para. 90: “cell data are directly read out to the nodes N21 of the second page buffer 200b);
and a memory controller (see e.g. FIG. 1: controller 110; see also para. 7: “…an externally provided memory controller to perform inspection or testing of write data”) coupled to the memory device and configured to control the memory device.
Regarding independent claim 13, Hosono teaches a method for operating
a memory device (see para. 3: “This invention relates…to an electrically rewritable non-volatile semiconductor memory device) comprising
an array of memory cell (FIG. 1: memory cell array 100), the array of memory cells comprising
a first memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC0) and a second memory cell (FIG. 2: memory cell array 100, (e.g.) memory cell MC1)
that are coupled to a page buffer circuit in a page buffer (FIG. 3: page buffer 200, first page buffer circuit 200a, and second page buffer circuit 200b),
each of the first memory cell and the second memory cell configured to store
N-bits data (FIG. 6: memory cell MC; see para. 58: “This memory cell MC stores a bit data”; see also para. 89),
the page buffer circuit (FIG. 1: read/write circuit (page buffer) 200) comprising
a sense out (SO) node (FIG. 3: output from pre-sense circuit Pre SA 31)
and a cache storage unit (FIG. 3: second page buffer circuit 200b; see also para. 52: “200b is for use as a cache which temporarily holds write/read data therein”),
the method comprising: suspending a program operation on the first memory cell (see e.g. FIG. 11) responsive to receiving a suspension command indicative of executing a read operation on the second memory cell (see e.g. FIG. 11);
controlling the page buffer circuit (FIG. 3: first page buffer circuit 200a) to store
suspended program information associated with a suspension of the program operation;
and performing the read operation on the second memory cell (see para. 90: “write operation is suspended; then, reading of…Row2…carried out while holding the write data in the first page buffer 200a”; see also FIG. 10A-H and e.g. FIG. 11),
comprising directly storing one of N-bits data of the second memory cell (see e.g. FIG. 10E: <Read from Row2 cells>)
into the cache storage unit (FIG. 3: second page buffer circuit 200b)
through the SO node (FIG. 3: output from pre-sense circuit Pre SA 31; see also para. 90: “cell data are directly read out to the nodes N21 of the second page buffer 200b).
Regarding claim 16, Hosono teaches the method of claim 13 (see prior paragraph regarding claim 13),
wherein performing the read operation on the second memory cell (FIG. 1: memory cells of memory cell array 100) is further comprises:
precharging (e.g. FIG. 4: first page buffer 200a, transistor 42; see also para. 55: “A precharge-use NMOS transistor 42 is provided at the sense node N0”) the SO node (FIG. 3: page buffer 200, output from pre-sense circuit Pre SA 31; see also FIG. 4: first page buffer 200a, node N0);
and storing an initial sensing result into the cache storage unit (see e.g. FIG. 11: operation at time t30-t32; see also FIG. 10A: <Read from Row1 cells>).
Figure 4 diagrams the configuration of the first page buffer 200a of Figure 3. Figure 3 shows that the first page buffer 200a and the second page buffer 200b are identical. Thus, when data is to be read out and stored in page buffer 200b during a copy write operation, the precharge-use transistor(s) of first page buffer 200a being also found in page buffer 200b meets the limitation of precharging of the SO node(s) of the relevant page buffer circuit during the reading operation as evident by the structural pre-charging capabilities of the page buffer circuits 200a and 200b.
Regarding claim 17, Hosono teaches the method of claim 16 (see prior paragraph regarding claim 16),
wherein performing the read operation on the second memory cell (see para. 90: “write operation is suspended; then, reading of…Row2…carried out”; see also FIG. 10A-H and e.g. FIG. 11) is further comprises:
applying a first sensing level to the second memory cell; and storing a first sensing result into the cache storage unit (FIG. 3: second page buffer circuit 200b) through the SO node (FIG. 3: output from pre-sense circuit Pre SA 31; see also para. 90: “cell data are directly read out to the nodes N21 of the second page buffer 200b).
Regarding claim 20, Hosono teaches the method of claim 13 (see prior paragraph regarding claim 13),
further comprising sensing each of the N-bits data of the second memory cell one by one through the SO node and the cache storage unit (FIG. 3: page buffer 200, output from pre-sense circuit Pre SA 31; see also FIG. 4: first page buffer 200a, node N0).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 2-3, 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono et al. (US 20030169630 A1) and further in view of Wan (CN-114168491-A, which was published 3/11/22; US 20230168820 is relied upon in the rejection as an equivalent English translation because it is from the same Patent family list).
Regarding claim 2, related memory system claim 12, and related method claim 14, Hosono teaches the claim limitations of the memory device of claim 1, the memory system claim 11, and the method of operation claim 13, respectively.
Hosono does not teach wherein the page buffer circuit (Hosono, FIG. 3: page buffer 200) further comprises a sensing storage unit, and the sensing storage unit is configured to store an inhibit information associated with the suspension of the program operation.
PNG
media_image1.png
514
771
media_image1.png
Greyscale
WAN teach the page buffer circuit (FIG. 2: page buffer 200) further comprises
a sensing storage unit (e.g. FIG. 2: first latch 111),
and the sensing storage unit is configured to store an inhibit information associated with the suspension of the program operation (WAN, see para. 49: “Specifically, first latch 111 may store information for distinguishing a memory cell to be inhibited from the memory cells based on a program verification voltage. That is, the information that distinguishes a memory cell to be programmed and a memory cell to be inhibited from each other may be stored in first latch 111”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory device of Hosono to incorporate WAN’s teachings of a page buffer circuit that further comprises a sensing storage unit configured to store an inhibit information associated with the suspension of the program operation. Hosono and WAN are analogous art to the claimed invention as both are directed at NAND Flash memory.
One of ordinary skill in the art would have been motivated to modify the memory device and page buffer circuit of Hosono according to the teachings of WAN to support a suspension of programming operation feature and a read operation during a suspension of a program operation due to the page buffer circuit locally retaining all the suspended program information. Additionally, the minimal latch design of the page buffer circuit taught by WAN would decrease the design and manufacturing cost of the memory device while supporting multi-level cell programming (WAN: "page buffer 200 may apply different bit line voltages to the memory cells to be programmed and memory cells to be inhibited by using the program/inhibit distinguishing information applied to the sensing node SO stored in first latch 111").
Regarding claim 3 and related method claim 15, Hosono teaches the claim limitations of the memory device of claim 1 and the method of operation claim 13, respectively.
Hosono does not teach wherein the page buffer circuit comprises N-1 data storage units and a bit line storage unit, and each of the N-1 data storage units is configured to store one of N-bits data of the first memory cell associated with the suspension of the program operation.
WAN teaches the page buffer circuit (WAN, FIG. 2: page buffer 200) comprises N-1 data storage units (WAN, see para. 45: “Each page buffer 200 may include at least a first latch 111, a second latch 112, and a dynamic latch 113”; see also para. 48: “each page buffer may further include a data latch (not shown in FIG. 2). Data latches are used to cache data to be programmed into the memory cell array. When the memory device is a triple-level cells (TLC)…correspondingly, the data latch may include three data latches”)
and a bit line storage unit (WAN, e.g. FIG. 2: second latch 112; see para. 50: “second latch 112 may store information for distinguishing a memory cell to be subjected to the first bit line forcing operation…from the memory cells not passing program verification…i.e., to distinguish the memory cells that are forced to operate via the first bit line and the memory cells that are not forced to operate via the first bit line”),
and each of the N-1 data storage units is configured to store one of N-bits data of the first memory cell (WAN, see para. 45: “Data latches are used to cache data to be programmed into the memory cell array”) associated with the suspension of the program operation.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory device of Hosono to incorporate WAN’s teachings of a page buffer circuit that further comprises a sensing storage unit configured to store an inhibit information associated with the suspension of the program operation. Hosono and WAN are analogous art to the claimed invention as both are directed at NAND Flash memory.
One of ordinary skill in the art would have been motivated to modify the memory device and page buffer circuit of Hosono according to the teachings of WAN to support a suspension of programming operation feature and a read operation during a suspension of a program operation due to the page buffer circuit locally retaining all the suspended program information. Additionally, the minimal latch design of the page buffer circuit taught by WAN would decrease the design and manufacturing cost of the memory device while supporting multi-level cell programming.
Claims 7, 8, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono et al. (US 20030169630 A1) and Hsu (US 20210012834).
Regarding claim 7 and 18, Hosono teaches the memory device of claim 6 and the method of operation of claim 17, from which claims 7 and 18 depend respectively
Hosono generally teach NAND memory utilizing a page buffer (see Fig. 4), where their NAND memory cells appear to be single bit (Fig. 8). In other words, Hosono, during a read operation would have been expected to perform the read operation by precharing its sense node (Fig. 4: N0, by precharge transistor 42) and then apply first sensing level to the single-level memory cell to distinguish between logic “0” and logic “1” (see Fig. 8 threshold voltage distributions indicative of single-level storage).
Hosono does not teach, to perform the read operation on the second memory cell, the control logic is further configured to: after the first sensing level is applied to the second memory cell, precharge the SO node; apply a second sensing level to the second memory cell; and store a second sensing result into the cache storage unit through the SO node.
Hsu teaches a multilevel NAND memory that stores 3 bits, or eight levels (see Figs 1A-1C as related to page buffer illustrated in Figure 2). Hsu illustrates conventional read operations for a TLC that involves applying a plurality of read voltages (see e.g., Fig. 1C: VR2, VR4, VR6 for determining bit D1, of the three bits D0-D2; see explanation at para. 59-63) in order to determine appropriate bits of TLC data, to hold in one of three latches (Fig. 2: 210a, 201b, 201c) indicative of the 3-bits read. Hsu explains the SA node is precharged (see para. 66: “the pre-charge device (205) is turned on to precharge the SA node (208)”), and then the isolation transistor 206 is connected to the bitline either causing the SA node to remain at VDD or discharge (see para. 66), after which the sensed result will be stored in the data latches.
In other words, as claimed, Hsu teaches:
“after the first sensing level is applied to the second memory cell” (see Fig. 1C: after VR2 is applied to WL), precharge the SO node (see Fig. 1C: time T3, where “bit line” is precharged, which also means the SA node is precharged as explained in para. 61 and 66);
“apply a second sensing level to the second memory cell” (Fig. 1C: VR4); and
“store a second sensing result into the cache storage unit through the SO node” (see para. 59-63 as related to Figures 1A-1C and Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Hsu’s background conventional read operation for TLC NAND memory to the teachings of Hosono, such that TLC memory is implemented so as to increase memory density and, for read operations of the implemented TLC memory, for each of the multiple read levels used to sense the TLC data, the sense node is precharged before data is sensed and then the data is sensed to be stored in a latch of the page buffer because it was a conventional read technique for TLC NAND memory previously known to ordinarily skilled NAND flash memory artisans.
Regarding claim 8 and 19, Hosono teaches the memory device of claim 6 and the method of operation of claim 17.
Hosono generally teach NAND memory utilizing a page buffer (see Fig. 4), where their NAND memory cells appear to be single bit (Fig. 8). In other words, Hosono, during a read operation would have been expected to perform the read operation by precharing its sense node (Fig. 4: N0, by precharge transistor 42) and thenapply first sensing level to the single-level memory cell to distinguish between logic “0” and logic “1” (see Fig. 8 threshold voltage distributions indicative of single-level storage).
Hosono does not teach, to perform the read operation on the second memory cell, the control logic is further configured to: after the second sensing level is applied to the second memory cell, precharge the SO node; apply a third sensing level to the second memory cell; and store a third sensing result into the cache storage unit through the SO node.
Hsu teaches a multilevel NAND memory that stores 3 bits, or eight levels (see Figs 1A-1C as related to page buffer illustrated in Figure 2). Hsu illustrates conventional read operations for a TLC that involves applying a plurality of read voltages (see e.g., Fig. 1C: VR2, VR4, VR6 for determining bit D1, of the three bits D0-D2; see explanation at para. 59-63) in order to determine appropriate bits of TLC data, to hold in one of three latches (Fig. 2: 210a, 201b, 201c) indicative of the 3-bits read. Hsu explains the SA node is precharged (see para. 66: “the pre-charge device (205) is turned on to precharge the SA node (208)”), and then the isolation transistor 206 is connected to the bitline either causing the SA node to remain at VDD or discharge (see para. 66), after which the sensed result will be stored in the data latches.
In other words, as claimed, Hsu teaches:
“after the second sensing level is applied to the second memory cell” (see Fig. 1C: after VR4 is applied to WL), precharge the SO node (see Fig. 1C: time T4, where “bit line” is precharged, which also means the SA node is precharged as explained in para. 61 and 66);
“apply a third sensing level to the second memory cell” (Fig. 1C: VR6); and
“store a third sensing result into the cache storage unit through the SO node” (see para. 59-63 as related to Figures 1A-1C and Figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Hsu’s background conventional read operation for TLC NAND memory to the teachings of Hosono, such that TLC memory is implemented so as to increase memory density and, for read operations of the implemented TLC memory, for each of the multiple read levels used to sense the TLC data, the sense node is precharged before data is sensed and then the data is sensed to be stored in a latch of the page buffer because it was a conventional read technique for TLC NAND memory previously known to ordinarily skilled NAND flash memory artisans.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHIM T PHUNG whose telephone number is (571)272-8524. The examiner can normally be reached Mon-Fri. 8:00am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/N.T.P./Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
Prosecution Insights