DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-15, & 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2012231078A hereafter referred to as Sato.
In regards to claim 1, Sato discloses
A multilayer electronic component, comprising:
a body (2 – fig. 1, 3, & 5; [0010]) including a dielectric layer (5 – fig. 5; [0010]), and internal electrode layers (3a-3c – fig. 5 & 8; [0012] & [0052]) disposed alternately in a first direction with the dielectric layer, and including first and second surfaces opposing each other in the first direction (2a & 2b – fig. 3 & 5; [0010]), third and fourth surfaces (2e & 2f – fig. 5 & 8; [0010]) connected to the first and second surfaces (2c & 2d – fig. 3 & 8; [0010]) and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; and
first and second external electrodes (4a & 4b – fig. 1; [0012]) disposed on the third and fourth surfaces, respectively,
wherein the internal electrode layer includes a first internal electrode layer (3a) and a second internal electrode layer (3c),
wherein the first internal electrode layer includes a first internal electrode (3a) including a first main portion (31 – fig. 8; [0046-0047]) and a first lead portion (32 – fig. 8; [0046-0047]) extending from the first main portion, exposed to the third surface and connected to the first external electrode, and a first dummy electrode (6 – fig. 8; [0025]) spaced apart from the first internal electrode, exposed to the third surface and connected to the first external electrode,
wherein the second internal electrode layer includes a second internal electrode (3c) including a second main portion (31 – fig. 8; [0046-0047] & [0052]) and a second lead portion (32 – fig. 8; [0046-0047] & [0052]) extending from the second main portion, exposed to the fourth surface and connected to the second external electrode, and a second dummy electrode (6 – fig. 8; [0025] & [0052]) spaced apart from the second internal electrode, exposed to the fourth surface and connected to the second external electrode,
wherein a size in the third direction of a portion of the first lead portion is smaller than a size in the third direction of the first main portion, and a size in the third direction of a portion of the second lead portion is smaller than a size in the third direction of the second main portion (fig. 8),
wherein the first dummy electrode does not overlap the second internal electrode in the first direction, and the second dummy electrode does not overlap the first internal electrode in the first direction (figs. 5 & 8),
wherein at least a portion of the first dummy electrode overlaps the first internal electrode in the second direction, and at least a portion of the second dummy electrode overlaps the second internal electrode in the second direction (fig. 4c & 8), and
wherein the first dummy electrode is disposed in only one of two opposing sides of the first lead portion in the third direction (fig. 8), and
the second dummy electrode is disposed in only one of two opposing sides of the second lead portion in the third direction (fig. 8; [0052]).
In regards to claim 2, Sato discloses
The multilayer electronic component of claim 1, wherein the first and second lead portions are disposed adjacently to one of the fifth and sixth surfaces (fig. 8).
In regards to claim 4, Sato discloses
The multilayer electronic component of claim 1, wherein sizes in the third direction of exposed portions of the first and second lead portions are smaller than average sizes in the third direction of the first and second main portions, respectively (fig. 8).
In regards to claim 5, Sato discloses
The multilayer electronic component of claim 1, wherein at least a portion of each of distances at which the first and second internal electrode and the first and second dummy electrode are spaced apart from each other, respectively, is substantially constant (fig. 8 – it is noted that the portions near the end surface have a distance that is substantially constant).
In regards to claim 6, Sato discloses
The multilayer electronic component of claim 1, wherein the first and second dummy electrodes are further exposed to one of the fifth and sixth surfaces (fig. 8).
In regards to claim 7, Sato discloses
The multilayer electronic component of claim 6, wherein the first external electrode is disposed to cover exposed portions of the first dummy electrode, and second external electrode is disposed to cover exposed portions of the second dummy electrode (fig. 8).
In regards to claim 8, Sato discloses
The multilayer electronic component of claim 1, wherein the internal electrode layer further includes a third internal electrode layer (3b – fig. 8) and a fourth internal electrode layer (3c having 3b design – fig. 5 & 8; [0052]),
wherein the third internal electrode layer includes a third internal electrode (3b) including a third main portion (31 – fig. 8; [0046-0047]) and a third lead portion (32 – fig. 8; [0046-0047]) extending from the third main portion, exposed to the third surface and connected to the first external electrode, and a third dummy electrode (6 – fig. 8; [0025] & [0052]) spaced apart from the third internal electrode, exposed to the third surface, and connected to the first external electrode,
wherein the fourth internal electrode layer includes a fourth internal electrode including a fourth main portion (31 – fig. 8; [0046-0047] & [0052]) and a fourth lead portion (32 – fig. 8; [0046-0047] & [0052]) extending from the fourth main portion, exposed to the fourth surface and connected to the second external electrode, and a fourth dummy electrode (6 – fig. 8; [0025] & [0052]) spaced apart from the fourth internal electrode, exposed to the fourth surface and connected to the second external electrode,
wherein a size in the third direction of a portion of the third lead portion is smaller than a size in the third direction of the third main portion, and a size in the third direction of a portion of the fourth lead portion is smaller than a size in the third direction of the fourth main portion (fig. 8),
wherein the third dummy electrode does not overlap the fourth internal electrode in the first direction, and the fourth dummy electrode does not overlap the third internal electrode in the first direction (fig. 5 & 8),
wherein at least a portion of the third dummy electrode overlaps the third internal electrode in the second direction, and at least a portion of the fourth dummy electrode overlaps the fourth internal electrode in the second direction (fig. 4c & 8), and
wherein the first lead portion is disposed closer to the fifth surface than the third lead portion, and the second lead portion is disposed closer to the fifth surface than the fourth lead portion (fig. 8).
In regards to claim 9, Sato discloses
The multilayer electronic component of claim 8, wherein the first internal electrode layer and the third internal electrode layer are symmetrical in the third direction with respect to a second direction axis (fig. 8), and
wherein the second internal electrode layer and the fourth internal electrode layer are symmetrical in the third direction with respect to the second direction axis (fig. 8; [0052]).
In regards to claim 10, Sato discloses
The multilayer electronic component of claim 8, wherein the first to second lead portions are disposed adjacently to one of the fifth and sixth surfaces (fig. 8).
In regards to claim 11, Sato discloses
The multilayer electronic component of claim 8, wherein each of the first to fourth dummy electrodes is disposed in one of two opposing sides of a corresponding one of the first to fourth lead portions in the third direction (fig. 8; [0052]).
In regards to claim 12, Sato discloses
The multilayer electronic component of claim 8, wherein sizes in the third direction of exposed portions of the first to fourth lead portions are smaller than average sizes in the third direction of the first to fourth main portions, respectively (fig. 8).
In regards to claim 12, Sato discloses
The multilayer electronic component of claim 8, wherein at least a portion of distances at which the first to fourth internal electrodes and the first to fourth dummy electrodes are spaced apart from each other is substantially constant (fig. 8 – it is noted that the portions near the end surface have a distance that is substantially constant).
In regards to claim 14, Sato discloses
The multilayer electronic component of claim 8, wherein the first to fourth dummy electrodes are further exposed to one of the fifth and sixth surfaces (fig. 8).
In regards to claim 15, Sato discloses
The multilayer electronic component of claim 14, wherein the first external electrode is disposed to cover exposed portions of the first and third dummy electrodes, and the second external electrode is disposed to cover exposed portions of the third and fourth dummy electrodes (fig. 8).
In regards to claim 17, Sato discloses
The multilayer electronic component of claim 1, wherein a size in the third direction of at least one of the first and second lead portions gradually decreases toward a surface of the body in the second direction, and a size in the third direction of at least one of the first and second dummy electrodes gradually increases toward said surface of the body in the second direction (fig. 8), and
the first lead portion and the first dummy electrode have inclined edges facing each other (fig. 8).
Claim(s) 1-2, 4-5, & 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP20011108783A hereafter referred to as Aoki.
In regards to claim 1, Aoki discloses
A multilayer electronic component, comprising:
a body (2 – fig. 1 & 7; [0021]) including a dielectric layer (5 – fig. 2; [0022]), and internal electrode layers (7C & 7D – fig. 5 & 7; [0032] & [0037]) disposed alternately in a first direction with the dielectric layer, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction (fig. 2, 5, & 7); and
first and second external electrodes (3A & 3B – fig. 5 & 7; [0037]) disposed on the third and fourth surfaces, respectively,
wherein the internal electrode layer includes a first internal electrode layer (7C) and a second internal electrode layer (7D),
wherein the first internal electrode layer includes a first internal electrode (7C) including a first main portion (13C – fig. 5; [0040]) and a first lead portion (14D – fig. 5; [0047]) extending from the first main portion, exposed to the third surface and connected to the first external electrode, and a first dummy electrode (15A – fig. 5; [0047]) spaced apart from the first internal electrode, exposed to the third surface and connected to the first external electrode,
wherein the second internal electrode layer includes a second internal electrode (7D) including a second main portion (13D – fig. 5; [0049]) and a second lead portion (14F – fig. 5; [0037]) extending from the second main portion, exposed to the fourth surface and connected to the second external electrode, and a second dummy electrode (15B – fig. 5; ][0038]) spaced apart from the second internal electrode, exposed to the fourth surface and connected to the second external electrode,
wherein a size in the third direction of a portion of the first lead portion is smaller than a size in the third direction of the first main portion, and a size in the third direction of a portion of the second lead portion is smaller than a size in the third direction of the second main portion (fig. 5),
wherein the first dummy electrode does not overlap the second internal electrode in the first direction, and the second dummy electrode does not overlap the first internal electrode in the first direction (figs. 5),
wherein at least a portion of the first dummy electrode overlaps the first internal electrode in the second direction, and at least a portion of the second dummy electrode overlaps the second internal electrode in the second direction (fig. 5; [0040]), and
wherein the first dummy electrode is disposed in only one of two opposing sides of the first lead portion in the third direction (fig. 5), and
the second dummy electrode is disposed in only one of two opposing sides of the second lead portion in the third direction (fig. 5).
In regards to claim 2, Aoki discloses
The multilayer electronic component of claim 1, wherein the first and second lead portions are disposed adjacently to one of the fifth and sixth surfaces (fig. 5).
In regards to claim 4, Aoki discloses
The multilayer electronic component of claim 1, wherein sizes in the third direction of exposed portions of the first and second lead portions are smaller than average sizes in the third direction of the first and second main portions, respectively (fig. 5).
In regards to claim 5, Aoki discloses
The multilayer electronic component of claim 1, wherein at least a portion of each of distances at which the first and second internal electrode and the first and second dummy electrode are spaced apart from each other, respectively, is substantially constant (fig. 5 – portion in the third direction has distance that is substantially constant).
In regards to claim 16, Aoki discloses
The multilayer electronic component of claim 1, wherein a size in the third direction of at least one of the first and second lead portions is substantially constant, and a size in the third direction of at least one of the first and second dummy electrodes is substantially constant (fig. 5).
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest (in combination with the other claim limitations) wherein at least one of the first and second lead portions has two stepped portions from a side edge of a corresponding one of the first and second main portions with reduced sizes in the third direction, and at least one of the first and second dummy electrodes has two stepped portions matching the two stepped portions of a corresponding one of the first and second lead portions with increased sizes in the third direction (claim 18).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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