DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new amendments do not teach in any references applied in the prior rejection of record.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa et al (US 20120174098, Tanikawa) in view of Gopal et al (US 20190173920, Gopal) and further in view of Okada et al (US 20160364349, Okada).
As to claim 1, Tanikawa discloses an operating system-based virtual interrupt handling method, comprising:
determining a first virtual central processing unit currently running (fig. 5-6 s104, s113 “is virtual CPU to be interrupted operating?”);
determining target configuration information (par. 88, “identifies the type of the interrupt request and the target to be interrupted”) corresponding to an interrupt request (“interrupt request”) from pre-configured interrupt configuration information (“accesses the interrupt request information”), and
execute an interrupt handler (VM scheduler 141) by using an interrupt controller (interrupt controller 106) based on the first virtual central processing unit and the target configuration information (par. 90 s105-109).
Tanikawa does not disclose the step of controlling a second virtual central processing unit to execute the interrupt handler. In the same field of art (virtual machine), Gopal discloses a method for deterministic load balancing of processing encapsulated encrypted data packets at a destination tunnel endpoint (par. 10). In one embodiment, Gopal discloses a selected virtual CPU (fig. 2, virtual CPU 225) executes an interrupt handler invoked by the kernel in response to an interrupt issued by a virtual NIC (par. 28, VNIC 226). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa and Gopal, by controlling a second virtual central processing unit to execute an interrupt handler. The motivation is to improve the reliablity and the efficiency of the system (par. 5).
Tanikawa does not disclose the interrupt configuration information being stored in an operating system kernel and indicating a mapping relationship between at least one interrupt type and a second virtual central processing unit for executing an interrupt handler. In the same field of art (virtual machine), Okada discloses a computer system that has a virtualization function module which notifies interrupt to a guest OS running on a virtual computer to which an I/O device that is suffering a failure is allocated (par. 5). In one embodiment, Okada discloses an interrupt configuration information (fig. 1 table 250, 260, 270) being stored in an operating system kernel (Note: Hypervisor 200 is in an OS kernel because it acts as a bridge between physical hardware 100 and guest OS 400) and indicating a mapping relationship (fig. 4, 5) between at least one interrupt type (“host side interrupt vector”, “guest-side interrupt vector”, or “vector type”) and a second virtual central processing unit for executing an interrupt handler (“guest OS”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal and Okada, by comprising the interrupt configuration information being stored in an operating system kernel and indicating a mapping relationship between at least one interrupt type and a second virtual central processing unit for executing an interrupt handler The motivation is to improve the performance of the system (par. 13).
As to claim 17, all the same elements of claim 1 are listed, but in a non-transistory computer readable storage form. Therefore, the supporting rationale of the rejection to claim 1 applies equally to claim 17.
As to claim 20, all the same elements of claim 1 are listed with further a processor (fig. 1, CPU 103) and a memory configured to store an instruction (memory 102) in a device form. Therefore, the supporting rationale of the rejection to claim 1 applies equally to claim 20.
Claims 2-3, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada and further in view of Zeng et al (US 20150127866, Zeng).
As to claim 2, Tanikawa/Gopal/Okada discloses the method according to claim 1, but does not disclose the limitations in claim 2. In the same field of art (machine virtualization), Zeng discloses methods for assigning one or more interrupts in a computing device (par. 3). In one embodiment, Zeng discloses the step of determining an interrupt identifier corresponding to the interrupt request (fig. 4 s404); determining an interrupt type based on the interrupt identifier (s406); and determining sub-configuration information corresponding to the interrupt type from the interrupt configuration information based on the interrupt type (par. 6s408, secure or non-secure interrupt, s502); and determining the target configuration information from the interrupt configuration information based on the interrupt type and the interrupt identifier (fig. 5 s504, s506). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Zeng. The motivation is to improve the performance of the system (par. 1).
As to claim 3, Tanikawa/Gopal/Okada/Zeng discloses the method according to claim 2, wherein the determining the target configuration information from the interrupt configuration information based on the interrupt type and the interrupt identifier comprises:
determining sub-configuration information corresponding to the interrupt type from the interrupt configuration information based on the interrupt type (Zeng, par. 6 s408, secure or non-secure interrupt, s502); and
determining the target configuration information from the sub-configuration information corresponding to the interrupt type based on the interrupt identifier (fig. 5 s504, s506).
As to claims 18-19, all the same elements of claims 2-3 are listed. Therefore, the supporting rationale of the rejection to claims 2-3 applies equally to claims 18-19.
Claims 4, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada and further in view of Nakahashi et al (US 20100106876, Nakahashi).
As to claim 4, Tanikawa/Gopal/Okada discloses the method according to claim 1, but does not disclose the limitations in claim 4. In the same field of art (machine virtualization), Nakahashi discloses a multiprocessor system including a plurality of processor units each transmitting an interrupt request signal (par. 9). In one embodiment, Nakahashi discloses that, in response to that a target configuration information comprises a second virtual central processing unit (fig. 2-4), determining an inclusion relationship between the first virtual central processing unit and the second virtual central processing unit (par. 33). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Nakahashi by, in response to that the target configuration information comprises the second virtual central processing unit, determining an inclusion relationship between the first virtual central processing unit and the second virtual central processing unit; and controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the inclusion relationship and the target configuration information. The motivation is to improve the reliability of the system (par 8).
As to claim 7, Tanikawa/Gopal/Okada/Nakahashi discloses the method according to claim 4, wherein the controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the inclusion relationship and the target configuration information comprises:
in response to that the inclusion relationship indicates that the first virtual central processing unit is same as the second virtual central processing unit (Nakahashi, fig. 4, par. 45. For instance, the priority order of CPU2 are same as CPU3’s when the interrupt request is from CPU1), controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the target configuration information (Gopal, par. 28).
As to claim 8, Tanikawa/Gopal/Okada/Nakahashi discloses the method according to claim 4, wherein the controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the inclusion relationship and the target configuration information comprises:
storing the target configuration information in response to that the inclusion relationship indicates that the first virtual central processing unit is different from the second virtual central processing unit (Nakahashi, fig. 2, par. 33. Note: The priorities of CPUs are different); and
in response to that the virtual central processing unit currently running is switched from the first virtual central processing unit to the second virtual central processing unit (“selected as the interrupt destination CPU” ), controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the target configuration information (Gopal, par. 28).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada/Zeng and further in view of Nakahashi.
As to claim 5, Tanikawa/Gopal/Okada/Zeng discloses the method according to claim 2, but does not disclose the limitations in claim 5. In the same field of art (machine virtualization), Nakahashi discloses a multiprocessor system including a plurality of processor units each transmitting an interrupt request signal (par. 9). In one embodiment, Nakahashi discloses that, in response to that a target configuration information comprises a second virtual central processing unit (fig. 2-4), determining an inclusion relationship between the first virtual central processing unit and the second virtual central processing unit (par. 33). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada/Zeng and Nakahashi by, in response to that the target configuration information comprises the second virtual central processing unit, determining an inclusion relationship between the first virtual central processing unit and the second virtual central processing unit; and controlling the second virtual central processing unit to execute the interrupt handler by using the interrupt controller based on the inclusion relationship and the target configuration information. The motivation is to improve the reliability of the system (par 8).
As to claim 6, all the same elements of claim 3 are listed, with further limitations in claim 5. Therefore, the supporting rationale of the rejection to claim 5 applies equally to claim 6.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Zeng/Okada/Nakahashi and further in view of Liang et al (US 20200097320, Liang).
As to claim 9, Tanikawa/Gopal/Okada/Zeng/Nakahashi discloses the method according to claim 5, but does not disclose the limitations in claim 5. In the same field of art (interrupt processing), Liang discloses an interrupt processing method in a multi-chip system (par. 4). In one embodiment, Liang further discloses, in response to that target configuration information comprises first interrupt information (par. 39 “interrupt request”), writing the first interrupt information into a register in the interrupt controller (“interrupt register 310 may store any of the interrupt requests”) and execute the interrupt handler by using the interrupt controller (“forwarded to the priority register 312”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada/Zeng/Nakahashi and Liang, by comprising: determining first interrupt information in the target configuration information; and writing the first interrupt information into a register in the interrupt controller, so that the interrupt controller controls the second virtual central processing unit to execute the interrupt handler. The motivation is to improve the reliability of the system (par. 2).
As to claim 10, all the same elements of claim 6 are listed, with further limitations in claim 9. Therefore, the supporting rationale of the rejection to claim 9 applies equally to claim 10.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada and further in view of Liang.
As to claim 11, Tanikawa/Gopal/Okada discloses the method according claim 1, wherein the second virtual central processing unit and the first virtual central processing unit are a same virtual central processing unit (Tanikawa, CPU 103), but does not disclose the limitations in claim 11. In the same field of art (interrupt processing), Liang discloses an interrupt processing method in a multi-chip system (par. 4). In one embodiment, Liang further discloses, in response to that target configuration information comprises second interrupt information (par. 39 “interrupt request”), writing the second interrupt information into a register in the interrupt controller (“interrupt register 310 may store any of the interrupt requests”) and execute the interrupt handler by using the interrupt controller (“forwarded to the priority register 312”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Liang, by comprising: in response to that the target configuration information comprises second interrupt information, writing the second interrupt information into a register in the interrupt controller; and controlling the first virtual central processing unit to execute the interrupt handler by using the interrupt controller. The motivation is to improve the reliability of the system (par. 2).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal//Okada/Zeng and further in view of Liang.
As to claim 12, Tanikawa/Gopal/Okada/Zeng discloses the method according claim 2, wherein the second virtual central processing unit and the first virtual central processing unit are a same virtual central processing unit (Tanikawa, CPU 103), but does not disclose the limitations in claim 12. In the same field of art (interrupt processing), Liang discloses an interrupt processing method in a multi-chip system (par. 4). In one embodiment, Liang further discloses, in response to that target configuration information comprises second interrupt information (par. 39 “interrupt request”), writing the second interrupt information into a register in the interrupt controller (“interrupt register 310 may store any of the interrupt requests”) and execute the interrupt handler by using the interrupt controller (“forwarded to the priority register 312”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Liang, by comprising: in response to that the target configuration information comprises second interrupt information, writing the second interrupt information into a register in the interrupt controller; and controlling the first virtual central processing unit to execute the interrupt handler by using the interrupt controller. The motivation is to improve the reliability of the system (par. 2).
As to claim 13, all the same elements of claim 3 are listed, with further limitations in claim 12. Therefore, the supporting rationale of the rejection to claim 12 applies equally to claim 13.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada and further in view of Cohen et al (US 20230128720, Cohen).
As to claim 14, Tanikawa/Gopal/Okada discloses the method according to claim 1, but does not disclose the limitations in claim 14. In the same field of art (machine virtualization), Cohen discloses a service call provider loaded within an operating system executing in a lower trust security zone (abstract). In one embodiment, Cohen further discloses during initialization of a virtual machine, invoking an operating system kernel (fig. 3, par. 51, OS kernel 111) through a user mode component of an operating system (user-mode process 124) to configure the configuration information in the operating system kernel (“to process the service call”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Cohen, by comprising: during initialization of a virtual machine, invoking an operating system kernel through a user mode component of an operating system to configure the interrupt configuration information in the operating system kernel. The motivation is to improve the data security of the system (par. 4).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanikawa in view of Gopal/Okada/Zeng and further in view of Cohen.
As to claim 15, Tanikawa/Gopal/Okada /Zeng discloses the method according to claim 2, but does not disclose the limitations in claim 15. In the same field of art (machine virtualization), Cohen discloses a service call provider loaded within an operating system executing in a lower trust security zone (abstract). In one embodiment, Cohen further discloses during initialization of a virtual machine, invoking an operating system kernel (fig. 3, par. 51, OS kernel 111) through a user mode component of an operating system (user-mode process 124) to configure the configuration information in the operating system kernel (“to process the service call”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanikawa/Gopal/Okada and Cohen, by comprising: during initialization of a virtual machine, invoking an operating system kernel through a user mode component of an operating system to configure the interrupt configuration information in the operating system kernel. The motivation is to improve the data security of the system (par. 4).
As to claim 16, all the same elements of claim 3 are listed, with further limitations in claim 15. Therefore, the supporting rationale of the rejection to claim 15 applies equally to claim 16.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
