Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the preliminary amendment filed on 03/05/2025.
Claim 1 is cancelled by the applicants.
Claims 2-19 are added by the applicants.
Claims 2-19 are pending.
Examiner’s Note
Please note that Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Objections
Claim 12-19 objected to because of the following informalities: claims 12-19 depends on claim 2 which is a different set of independent claim rather claims 12-19 should have been dependent on claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 8-13, 15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPN 20100122105 to Arslan et al.
Per claim 2:
Arslan discloses:
2. (New) A method performed using a compiler for a hardware synchronous processor, the method comprising:
processing an input program received by the compiler (paragraph [0051] “a front end module adapted to receive the program instructions”; paragraph [0131] “the standard GNU C Compiler (gcc) is used to compile C/C++ code 50 into assembly format 52”; paragraph [0145] “front end 610 of the RICA compiler is an instruction parser that deals with instructions such as addition, logic, div, shift, multiply”);
generating, based on the input program, timing information used by the synchronous processor to execute an operation corresponding to an instruction (paragraph [0124] “amount of clock cycles the RRC waits for before generating the Enable signal is configurable by the decoder 11 as part of the array's configuration instruction 10”; paragraph [0148] “resource and time constraints are given in the machine description 616 where pre-scheduling estimated routing times are utilized and post-scheduling the routing time delays from VPR are used”);
generating, based on the timing information, instructions used by the synchronous processor to execute operations of the input program the include computing an inference (paragraph [0139] “Each netlist contains a block of instructions that will be executed in a single clock cycle”; paragraph [0153] “VLIW DSP can only execute independent instructions in parallel while RICA can execute both independent and dependent assembly instructions in the same clock cycle because it allows connections in series”); and
scheduling when the instructions and the operations will be executed by the synchronous processor based on a constraint of the synchronous processor (paragraph [0148] “the scheduling and chaining of operations affects the register reuse, the scheduling algorithm also performs register assignment. The resource and time constraints are given in the machine description 616 where pre-scheduling estimated routing times are utilized and post-scheduling the routing time delays from VPR are used”; paragraph [0154] “Scheduling is a critical task in this process. Scheduling partitions the Control Data Flow Graph (CDFG) into time steps thereby generating a scheduled CDFG mode”).
Per claim 3:
Arslan discloses:
3. (New) The method of claim 2, wherein the input program comprises a set of operations and processing the input program comprises:
generating an intermediate representation of the input program by traversing dependencies between program nodes that correspond to operations in the set of operations of the input program (paragraph [0138] “the high-level compiler 604 takes the high-level code 602 and transforms it into an intermediate assembly language format 60”; paragraph [0186] “scheduler is the assembly code or other intermediate representation, a dependence graph (DG) is generated by removing the registers to represent instruction dependences”).
Per claim 4:
Arslan discloses:
4. (New) The method of claim 3, wherein generating the intermediate representation comprises:
assigning a respective clock cycle value to each operation in the set of operations of the input program (paragraph [0120] “assembly code of a program is sliced into blocks of instructions that are executed in a single variable length clock cycle”; paragraph [0192] “CPRS scheduling, nodes with the greatest critical-path lengths are selected to be scheduled at cycle t”).
Per claim 6:
Arslan discloses:
6. (New) The method of claim 4, wherein each respective clock cycle value that is assigned to a corresponding operation indicates when that corresponding operation will be executed by the synchronous processor (paragraph [0147] “computing priories in a sophisticated way, they try to schedule the most critical cells first, and to assign them to the right resource. LS usually employ a priority vector to determine what tasks to consider first”).
Per claim 8:
Arslan discloses:
8. (New) The method of claim 2, wherein the constraint is a clock timing constraint for executing the input program on the synchronous processor (paragraph [0124] “amount of clock cycles the RRC waits for before generating the Enable signal is configurable by the decoder 11 as part of the array's configuration instruction 10”; paragraph [0148] “time constraints include not only the programmable computational unit delay but also the routing delays”).
Per claim 9:
Arslan discloses:
9. (New) The method of claim 8, further comprising:
generating the clock timing constraint based on clock latency values for each respective operation of the input program (paragraph [0148] “resource and time constraints are given in the machine description 616 where pre-scheduling estimated routing times are utilized and post-scheduling the routing time delays from VPR are used”).
Per claim 10:
Arslan discloses:
10. (New) The method of claim 2, wherein the constraint is a clock timing constraint that specifies when particular operations in the set of operations must occur relative to other operations in the set of operations, when the set of operations is executed on the synchronous processor (paragraph [0147] “the precedence relations also need to be respected in list scheduling. All operations, whose predecessors in the DFG have completed their executions at a certain cycle t, are put in the so-called ready list R[t]”).
Claims 11-13 and 15 and 17-19 is/are the method claim corresponding to apparatus/system claims 1-4, 6 and 8-10 respectively and rejected under the same rational set forth in connection with the rejection of claims 1-4, 6 and 8-10 respectively, as noted above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 7, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 20100122105 to Arslan et al. in view of USPN 20060004997 et al.
Per claim 2:
Arslan discloses:
5. (New) The method of claim 3, wherein generating the intermediate representation comprises, for a subsequent operation in the set of operations that precedes a first operation:
assigning a clock cycle value to the subsequent operation based on:
i) a dependency between the first operation and the subsequent operation (paragraph [0131] “analysing the dependencies between them. Dependent program instructions are connected serially and independent program instructions are connected in parallel in the netlists”).
Arslan does not explicitly disclose ii) a cycle latency of a node that corresponds to the first operation.
However, Mykland discloses in an analogous computer system ii) a cycle latency of a node that corresponds to the first operation (Paragraph [0537] “creates a block operation that will take up the latency and similarly tries to schedule it earlier in the execution chain so the data will be available when the latency stall would have been hit”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of ii) a cycle latency of a node that corresponds to the first operation as taught by Mykland into the method of reconfiguring processor as taught by Arslan. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of ii) a cycle latency of a node that corresponds to the first operation to provide an efficient technique to perform reprogrammable tasks so as to fulfill the requirements of general purpose computers as suggested by Mykland (paragraph [0002]).
Per claim 7:
The rejection of claim 2 is incorporated and further Arslan does not explicitly disclose i) the input program is latency insensitive; and ii) the compiler is operable to compile the latency insensitive program for different underlying hardware designs of the synchronous processor.
However, Mykland discloses in an analogous computer system i) the input program is latency insensitive (Paragraph [0537] “creates a block operation that will take up the latency and similarly tries to schedule it earlier in the execution chain so the data will be available when the latency stall would have been hit”); and ii) the compiler is operable to compile the latency insensitive program for different underlying hardware designs of the synchronous processor (paragraph [0008] “the operating system executed by the integrated circuit computing device may be MICROSOFT NT, MICROSOFT WINDOWS 98, MAC O/S 10, LINUX, or another suitable operating system known in the art”).
The feature of providing disclose i) the input program is latency insensitive; and ii) the compiler is operable to compile the latency insensitive program for different underlying hardware designs of the synchronous processor would be obvious for the reasons set forth in the rejection of claim 5.
Claims 14 and 16 is/are the method claim corresponding to apparatus/system claims 5 and 7 respectively and rejected under the same rational set forth in connection with the rejection of claims 5 and 7 respectively, as noted above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Related cited arts:
Graillat, Amaury, et al. "Parallel code generation of synchronous programs for a many-core architecture." 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018. pp. 1139-1142.
Carloni, Luca P., et al. "A methodology for correct-by-construction latency insensitive design." 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No. 99CH37051). IEEE, 1999. pp. 309-315.
Carloni, Luca P. "From latency-insensitive design to communication-based system-level design." Proceedings of the IEEE 103.11 (2015): pp. 2133-2151.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Satish Rampuria whose telephone number is 571-272-3732. The examiner can normally be reached on Monday-Friday from 8:30 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do, can be reached at telephone number 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Satish Rampuria/Primary Examiner, Art Unit 2193
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