Prosecution Insights
Last updated: May 29, 2026
Application No. 18/930,873

READ RETRY METHOD FOR ENHANCING READ PERFORMANCE AND STABILITY OF 3D NAND MEMORY

Final Rejection §DP
Filed
Oct 29, 2024
Priority
Aug 16, 2022 — continuation of 12/169,640
Examiner
DUNCAN, MARC M
Art Unit
2113
Tech Center
2100 — Computer Architecture & Software
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
9m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
738 granted / 849 resolved
+31.9% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
7 currently pending
Career history
858
Total Applications
across all art units

Statute-Specific Performance

§101
8.8%
-31.2% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
20.0%
-20.0% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 849 resolved cases

Office Action

§DP
FINAL REJECTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-3 and 12-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 13 of U.S. Patent No. 12169640. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘640 claims contain all teachings of the instant claims and therefore anticipate the instant claims. Claim 1 is exemplary: Instant claim ‘640 claim 3 Explanation (as needed) A memory system, comprising: one or more memory devices configured to store data; and a memory controller coupled to the one or more memory devices and configured to: A memory system, comprising: one or more memory devices configured to store data; and a memory controller coupled to the one or more memory devices and configured to: same perform a read operation at a portion of the one or more memory devices; a read operation performed at a portion of the one or more memory devices same in response to a failure of the read operation, access a set of values of a set of effectors of the read operation associated with a trigger portion, wherein the trigger portion comprises one or more memory blocks or one or more memory pages associated with the portion of the one or more memory devices where the read operation failed, and the trigger portion is a designated portion of the one or more memory devices where sensing the set of values of the set of effectors is performed; detect a failure of a read operation; determine a trigger portion closest to the portion of the one or more memory devices where the failure of read operation is detected, wherein the trigger portion is one or more memory blocks or one or more memory pages, and wherein the trigger portion is a designated portion on the memory system where sensing and storing a set of values of effectors is performed; access the set of values of a set of effectors of the read operation associated with the trigger portion Removed elements of the ‘640 claim based on the set of values of the set of effectors of the read operation, select one or more read retry routines from a plurality of read retry routines; analyze the set of values that correspond to the set of effectors of the read operation; select one or more read retry routines from a plurality of read retry routines based on the analyzing Removed elements of the ‘640 claim and perform the selected one or more read retry routines at the portion of the one or more memory devices using one or more adjusted read voltages, perform the selected one or more read retry routines corresponding to each effector of the set of effectors of the read operation at the portion of the one or more memory devices using the adjusted read voltage corresponding to each effector of the set of effectors to negate the failure of the read operation. Broadened by reciting “one or more” instead of “each” wherein each of the selected one or more read retry routines corresponds to at least one effector of the set of effectors, one or more read retry routines corresponding to each effector of the set of effectors Broadened by reciting “one or more” instead of “each” and each of the one or more adjusted read voltages corresponds to one of the selected one or more read retry routines. using the adjusted read voltage corresponding to each effector of the set of effectors to negate the failure of the read operation. Broadened by reciting “one or more” instead of “each” perform at least one read retry routine of the one or more read retry routines with an adjusted pre-pulse duration different from a pre-pulse duration used in the failed read operation. perform a read retry routine of the one or more read retry routines with an adjusted pre-pulse duration different from a pre-pulse duration used in the failed read operation. Broadened by reciting “at least one” instead of “a” Claims 5, 6, 8-10, 16, 17, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 13 of U.S. Patent No. 12169640 in view of Takizawa et al. (2021/0082528). Claims 3 and 13 of the ‘640 patent teach all limitations of the instant claims except: wherein the sensing of the set of values comprises assigning a time stamp to a past programming event at the portion of the one or more memory devices; wherein the sensing of the set of values comprises sensing a temperature at the portion of the one or more memory devices; wherein the one or more memory devices comprise a three-dimensional (3D) NAND memory device; the set of values of the set of effectors comprises a time stamp of a past programming event at the portion of the one or more memory devices; the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a time-based effector of the read operation; the set of values of the set of effectors comprises a temperature at the portion of the one or more memory devices; and the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a temperature-based effector of the read operation. Takizawa teaches: wherein the sensing of the set of values comprises assigning a time stamp to a past programming event at the portion of the one or more memory devices [par 105 – the programming time is stored]; wherein the sensing of the set of values comprises sensing a temperature at the portion of the one or more memory devices [par 105, 113 – temperatures are sensed]; wherein the one or more memory devices comprise a three-dimensional (3D) NAND memory device [par 25, 99]; the set of values of the set of effectors comprises a time stamp of a past programming event at the portion of the one or more memory devices [par 105]; the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a time-based effector of the read operation [par 85, 112-114]; the set of values of the set of effectors comprises a temperature at the portion of the one or more memory devices [par 105, 114]; and the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a temperature-based effector of the read operation [par 85, 112-114]. It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the sensing and read retry routine teachings of Takizawa with the sensing and read retry routine teachings of the ‘640 claims because Tazizawa teaches that these sensing and read retry routine teachings cover three typical events that might largely affect a variation in threshold voltage [par 70]. Claims 7, 11, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 13 of U.S. Patent No. 12169640 in view of Hung (2019/0354314). Claims 3 and 13 of the ‘640 patent contain all teachings of the instant claim except a read count as one of the effectors to be sensed and consider when selecting a read retry routine. Hung explicitly teaches that read counts are an effector that should be accounted for to improve read retry selection [par 25, 30, 36-38 – descriptions of various factors that affect reading errors and can be mitigated with selection of particular read retry routines]. It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the read count of Hung with the effectors of the instant claims because Hung teaches that accounting for degradation from read count allows for faster selection of a more appropriate read retry routine, which reduces latency and prevents additional degradation, among other benefits [par 35]. Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 12169640 in view of Tuers et al. (2016/0054937). Claim 13 of the ‘640 patent contains all teachings of the instant claim except for a non-transitory computer-readable medium have instructions that, when executed, cause a method to be performed. Tuers teaches a non-transitory computer-readable medium have instructions that, when executed, cause a method to be performed [par 78]. It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the non-transitory CRM of Tuers with the method of the ‘640 patent claim because the CRM allows the benefits of the claimed method to be realized. Claims 21 and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 12169640 in view of Takizawa and Tuers. Claim 13 of the ‘640 patent contains all teachings of the instant claim except: wherein the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a time-based effector of the read operation; and wherein the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a temperature-based effector of the read operation. Takizawa teaches: wherein the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a time-based effector of the read operation [par 85, 112-114]; and wherein the selected one or more read retry routines comprises a read retry routine that uses a read voltage that corresponds to a temperature-based effector of the read operation [par 85, 112-114]. It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the sensing and read retry routine teachings of Takizawa with the sensing and read retry routine teachings of the ‘640 claims because Tazizawa teaches that these sensing and read retry routine teachings cover three typical events that might largely affect a variation in threshold voltage [par 70]. ‘640-Takizawa does not explicitly teach: a non-transitory computer-readable medium have instructions that, when executed, cause a method to be performed. Tuers teaches a non-transitory computer-readable medium have instructions that, when executed, cause a method to be performed [par 78]. It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the non-transitory CRM of Tuers with the ‘640-Takizawa because the CRM allows the benefits of the claimed method to be realized. Response to Arguments Applicant’s arguments, see page 8 of the remarks, filed 3/31/26, with respect to the outstanding 35 USC 103 rejection have been fully considered and are persuasive in light of the amendments to the claims. The rejection has been withdrawn. Applicant's arguments filed 3/31/26 with respect to the double patenting rejection have been fully considered but they are not persuasive. Merely amending the claims does not render the nonstatutory double patenting rejection moot. The claims continue to have a double patenting conflict with the 12169640 patent and the rejection has been updated to reflect the changes to the claim recitations based on the amendment. The examiner suggests filing of a terminal disclaimer to obviate the rejection and expedite prosecution of the application. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC M DUNCAN whose telephone number is (571)272-3646. The examiner can normally be reached M-F: 730am-9am, 10am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARC DUNCAN/Primary Examiner, Art Unit 2113
Read full office action

Prosecution Timeline

Oct 29, 2024
Application Filed
Dec 09, 2025
Non-Final Rejection (signed) — §DP
Jan 16, 2026
Non-Final Rejection mailed — §DP
Mar 31, 2026
Response Filed
May 22, 2026
Final Rejection mailed — §DP (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+7.4%)
2y 4m (~9m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 849 resolved cases by this examiner. Grant probability derived from career allowance rate.

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