Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the amendment filed on August 21,2026.
2. Claims 1-11 are pending and has been examined.
3. Claim rejection has been withdrawn.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 09/01/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 10/29/2024 are acceptable.
Response to Arguments
Applicants’ arguments filed 09/01/2026 have been fully considered but they are not persuasive. Applicant argues that Wong further fails to disclose the claimed phase reference signal. Wong's frequency selector 540 is arranged to "select between input reference frequency signal FREF INI and input reference frequency signal FREF _ IN2 to provide reference frequency signal FREF." Wong further explains that the input reference frequency signals may be selected such that the frequency associated with FREF _ INI is an integer multiple of, or evenly divisible by, the frequency associated with FREF IN2. Accordingly, Wong's FREF is a selected reference frequency obtained from predetermined input reference frequencies. Wong then adds JITTER to the selected FREF to obtain FJIT. This is not equivalent to the claimed phase reference signal participating in the generation of a first driving signal together with the phase jitter signal and the output phase signal of the inverter circuit. In the claimed invention, the phase reference signal is part of a phase-based control relationship. Its corresponding frequency behavior can vary depending on operating conditions of the inverter system, including, for example, output voltage, load condition, transformer
coupling condition, and/or other system conditions. Therefore, the claimed phase reference signal cannot simply be equated with Wong's selected FREF merely because both may be associated with a frequency. The difference between the claimed invention and Wong is further demonstrated by their respective control behavior.
However, examiner respectively disagree that a combination of DU and Jiang broadly reads the claim limitations.
Du discloses a phase-locked loop controller (FIG. 9, dithering circuitry 84) configured to output a first driving signal (optimized modulating waveform) according to a phase jitter signal (Fig. 9: the dithering circuitry 84 is configured to receive a Max frequency Jitter constraint) and an output phase signal of the inverter circuit (the dithering circuitry 84 is configured to receive TX parameters which includes a current, voltage and duty cycle from inverter 61 are equivalent to output phase signal) ; and controlling the inverter circuit by the first driving signal (optimized modulating waveform) but fails to discloses a phase reference signal.
Whereas Wong discloses first driving signal is generated according to a phase jitter signal and a phase reference signal (Fig. 5 shows jitter circuit 550 is configured to receive jitter signal (JITTER) and reference signal (FREF) and a duration controller 530 is generated Durations signal based on jitter signal (JITTER) and reference signal (FREF) , see col. 8, lines 34-41. Furthermore, Wong discloses a phase lock loop (PLL) to generate an output signal (Duration) with a consistent phase and frequency to control the regulator 100/500 see col. 3,lines 56-65 and col. 6, lines 57-67).
Examiner noted that a Jitter circuit 550 is arranged to receive JITTER signal with reference signal FREF and provide FJIT signal to pulse duration controller 530 . The pulse duration controller 130/530 is arranged to receive reference frequency signal FJIT and switch control signal SCTL to determine or control the switching frequency of regulator output circuitry 180/580, as part of another control loop. Both the invention and the references are configured to regulate/ control the phase loop of the power converter based on the phase jitter signal, phase reference signal and an output phase signal.
Therefore, a combination of DU and Wong discloses a phase jitter signal ( DU; Max frequency Jitter constraint is equivalent phase jitter signal), an output phase signal (DU: TX parameters which includes a current, voltage and duty cycle from inverter 61 are equivalent to output phase signal ) and phase reference signal (Wang: Jitter circuit 550 is arranged to receive signal JITTER with reference signal FREF and configured to provide signal FJIT ) are proper rejection. Furthermore, Wang discloses pulse duration controllers may be suitably employed. For example, digital counters, phase lock loop (PLL) circuitry, microprocessors, microcontrollers, other digital or analog logic, and/or the like, may be employed instead of the illustrated phase duration controller, see col. 6 lines 57-67.
Furthermore, applicant whole argument is by attacking second reference which is Wang. Applicant relying on features absent from the explicit claim languages are unpersuasive. It is improper arguing not explicitly recited in the claim languages.
For the above reasons, the examiner respectfully submits that the rejection is proper. Therefore, the rejection has been maintained.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Again, it is the Examiner’s position that Applicant has not yet submitted claims drawn to limitations, which define the operation and apparatus of Applicant’s disclosed invention in manner, which distinguishes over the prior art. As it is Applicant’s right to continue to claim as broadly as possible their invention. It is also the Examiner’s right to continue to interpret the claim language as broad as reasonable. It is the Examiner’s position that the detailed functionality that allows for Applicant’s invention to overcome the prior art used in the rejection, fails to differentiate in detail how these features are unique. Therefore, it is advised that, in order to further expedite the prosecution of the application in response to this action, Applicant should amend the base claims to describe in more narrow detail the true distinguishing features of Applicant’s claimed invention.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Patole “20230047448” in a view of Wong “7782036”.
In re to claim 1 Patole discloses a power conversion device (Figs. 1-9 : wireless power system), comprising: a first Direct Current (DC)-to-DC converter (Figs. 2: wireless power circuitry in system 8), comprising a primary side circuit (12) , a secondary side circuit (24) and a transformer (Fig. 2 winding 36 and 48) , wherein the transformer is configured to transfer energy between the primary side circuit (12) and the secondary side circuit (24), and the primary side circuit comprises an inverter circuit (61) ; and a control unit ( 16), comprising a phase-locked loop controller (FIG. 9, dithering circuitry 84) configured to output a first driving signal (optimized modulating waveform) according to a phase jitter signal (Fig. 9: the dithering circuitry 84 is configured to receive a Max frequency Jitter constraint) and an output phase signal of the inverter circuit (the dithering circuitry 84 is configured to receive TX parameters which includes a current, voltage and duty cycle from inverter 61 are equivalent to output phase signal) ; and controlling the inverter circuit by the first driving signal (optimized modulating waveform) but fails to discloses a phase reference signal.
Whereas Wong discloses first driving signal is generated according to a phase jitter signal and a phase reference signal (Fig. 5 shows jitter circuit 550 is configured to receive jitter signal (JITTER) and reference signal (FREF) and a duration controller 530 is generated Durations signal based on jitter signal (JITTER) and reference signal (FREF) , see col. 8, lines 34-41. Furthermore, Wong discloses a phase lock loop (PLL) see col. 3,lines 56-65 and col. 6, lines 57--7).
Therefore, it would have been obvious to one ordinary skilled person in the art before the filing date of the invention to have modified the dithering circuitry 84 of Patole to include reference signal (FREF) as taught by Wong because it may reduce the peak magnitude of the switching noise by spreading the switching noise over a range of frequencies. Further, this may enable reduction of the EMI generated by regulator 500, see col. 8, lines 34-41.
In re to claim 9 Patole discloses a method for controlling a power conversion device (Figs. 1-9) , wherein the power conversion device (Fig. 1-2) comprises: a first Direct Current (DC)-to-DC converter (Figs. 2: wireless power circuitry in system 8), comprising a primary side circuit (12) , a secondary side circuit (24) and a transformer (Fig. 2 winding 36 and 48) , wherein the transformer is configured to transfer energy between the primary side circuit (12) and the secondary side circuit (24) , and the primary side circuit comprises an inverter circuit (61) ; and a control unit (16) , comprising a phase-locked loop controller (FIG. 9, dithering circuitry 84 ) , wherein the method comprises: generating, by the phase-locked loop controller (84), a first driving signal (optimized modulating waveform), according to a phase jitter signal (Fig. 9: Max frequency Jitter constraint) and an output phase signal of the inverter circuit (TX parameters [current, voltage and duty cycle are equivalent to output phase signal of inverter 61 ) ; and controlling the inverter circuit by the first driving signal (optimized modulating waveform) but fails to discloses a phase reference signal.
Whereas Wong discloses first driving signal is generated according to a phase jitter signal and a phase reference signal (Fig. 5 shows jitter circuit 550 is configured to receive jitter signal (JITTER) and reference signal (FREF) and a duration controller 530 is generated Durations signal based on jitter signal (JITTER) and reference signal (FREF) , see col. 8, lines 34-41. Furthermore, Wong discloses a phase lock loop (PLL) see col. 3,lines 56-65 and col. 6, lines 57--7).
Therefore, it would have been obvious to one ordinary skilled person in the art before the filing date of the invention to have modified the dithering circuitry 84 of Patole to include reference signal (FREF) as taught by Wong because it may reduce the peak magnitude of the switching noise by spreading the switching noise over a range of frequencies. Further, this may enable reduction of the EMI generated by regulator 500, see col. 8, lines 34-41.
7. Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Patole “20230047448” in a view of Wong “7782036” further in a view of Du “20190058357”.
In re to claim 6, Patole as modified discloses (Figs. 1-9) the control unit (16) discloses an input sampling unit (Measurement circuitry 41) and but fails to discloses a power control unit and the input sampling unit is configured to acquire an input power feedback value of the first DC-to-DC converter; and the power control unit is configured to generate, according to a primary side power command and the input power feedback value of the first DC-to-DC converter, a first duty cycle or a first phase shift angle to act on the first driving signal to generate a third driving signal.
Whereas Du, discloses Fig. 4A-6: the detecting unit 25 (equivalent to input sampling unit) comprises a voltage detecting circuit 251a, a current detecting circuit 252a and a multiplier 253 a voltage detecting circuit 251a and the current detecting circuit 252a are connected with the input terminals of the input capacitor C.sub.in and the first control unit 26 (equivalent to power controller) judges that the input power signal is higher than the reference input power signal, the first control unit 26 generates the control signal with an increased switching frequency, a decreased duty cycle or an increased shifted phase angle, see prag.0034).
Therefore, it would have been obvious to one ordinary skilled person in the art before the filing date of the invention to have modified the wireless power system of Patole to include detecting unit 25 and first controller 26 as taught by Du because the input power of the transmitter unit is adjusted, and an output ripple or a magnitude of the output of the receiver unit is adjusted, thus an output ripple is reduced, see abstract, parag.0004 and 0068.
8. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Patole “20230047448” in a view of Wong “7782036” further in a view of Jiang “20220085649”.
In re to claim 8, Patole as modified discloses (Figs. 1-9) wherein the control unit (16) but fails to discloses further comprises: a second DC-to-DC converter, coupled between the first DC-to-DC converter and a load.
Whereas Jiang discloses a wireless power transmission apparatus (Fig.5: shows power regulation unit 30 is coupled between the receiving unit 20 and load. Examiner noted that the power regulation unit comprises any one of a buck circuit, a boost circuit, or a buck-boost circuit., see, parag.0096 and claim 12)
Therefore, it would have been obvious to one ordinary skilled person in the art before the filing date of the invention to have modified the wireless power system of Patole to include power regulation unit 30 as taught by Jiang the power regulation unit 30 to regulate the output signal of the wireless power transmission apparatus, so that the thereby reducing the current or voltage of the transmitting unit 10, reducing the loss, and improving the efficiency of the apparatus and the thermal stress, see prag.0121.
Allowable Subject Matter
9. Claims 2, 7, 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to because the prior art fail to discloses the power conversion device to including the limitation of “a pre-regulator, coupled between the first DC-to-DC converter and a power supply, and having a first voltage gain; the first DC-to-DC converter has a second voltage gain; and when the second voltage gain changes, the pre-regulator is configured to make the first voltage gain change inversely.”
Claim 7 is objected because the prior art fail to discloses the method for controlling power conversion device to including the limitation of “the control unit further comprises an output sampling unit and a second power command jitter unit; the output sampling unit is configured to acquire output ripple information of the first DC-to-DC converter; the second power command jitter unit is configured to generate a power command jitter signal based on the output ripple information of the first DC-to-DC converter, and send the power command jitter signal to the power control unit to make the power control unit superimpose a duty cycle or a phase shift angle of the power command jitter signal on a first duty cycle or the first phase shift angle of a power control signal to generate a fourth driving signal; and the power command jitter signal and the phase jitter signal have the same frequency and the same or opposite phases, and an amplitude of the power command jitter signal is determined based on the output ripple information of the first DC-to-DC converter. ”
Claim 10 is objected to because the prior art fail to discloses the method for controlling power conversion device to including the limitation of “a pre-regulator, coupled between the first DC-to-DC converter and a power supply, and having a first voltage gain; the first DC-to-DC converter has a second voltage gain; and when the second voltage gain changes, the pre-regulator is configured to make the first voltage gain change inversely.”
Claim 11 is objected to because the prior art fail to discloses the method for controlling power conversion device to including the limitation of “ a duty cycle jitter unit coupled between a pre-regulator and a pre-regulator controller, and the duty cycle jitter unit is further connected to an output sampling unit; the method for controlling the power conversion device further comprises: generating, by the duty cycle jitter unit, a duty cycle jitter signal based on output ripple information of the first DC-to-DC converter, wherein the output ripple information of the first DC-to-DC converter is acquired by the output sampling unit; and superimposing, by the duty cycle jitter unit, the duty cycle jitter signal on a control signal of the pre-regulator controller to generate a second driving signal; wherein the duty cycle jitter signal and the phase jitter signal have the same frequency and the same or opposite phases, and an amplitude of the duty cycle jitter signal is determined based on the output ripple information of the first DC-to-DC converter.”
Claims 3-5 dependent on claim 2, thus are also objected to because of their dependency.
Conclusion
10. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
Prosecution Insights