DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on October 30, 2024. These drawings are acceptable.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 line 8, “electrode portion the second” should be, “electrode portion to the second”.
Claim 8 line 9, “the second inner electrode” should be, “the second inner electrode layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP Publication 2005-340371 to Matsumoto et al. (hereinafter Matsumoto; see also provided machine translation).
Claim 1
Matsumoto (FIG. 1-6) discloses a through-type multilayer ceramic capacitor comprising:
a multilayer body (20) including a plurality of dielectric layers (12-13) which are laminated, and a plurality of inner electrode layers (2-3) laminated on the dielectric layers (12-13), the multilayer body (20) including a first main surface (top) and a second main surface (bottom) which oppose each other in a lamination direction, a first side surface (left side) and a second side surface (right side) which oppose each other in a width direction orthogonal or substantially orthogonal to the lamination direction, a first end surface (front side) and a second end surface (back side) which oppose each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction;
a first inner electrode layer (2) among the plurality of inner electrode layers (2-3) extends to the first end surface (front side) and the second end surface (back side);
a second inner electrode layer (3) among the plurality of inner electrode layers (2-3) extends to the first side surface (left side) and the second side surface (right side);
a first outer electrode (21) located on the first end surface (front side) and connected to the first inner electrode layer (2);
a second outer electrode (22) located on the second end surface (back side) and connected to the first inner electrode layer (2);
a third outer electrode (24) located on the first side surface (left side) and connected to the second inner electrode layer (3); and
a fourth outer electrode (23) located on the second side surface (right side) and connected to the second inner electrode layer (3); wherein
the first outer electrode (21) includes a first plating layer (46) located on the first end surface (front side), and a first charging electrode (45) located on the first end surface (front side) and including a length shorter than a length of the first plating layer (46) in the width direction (see FIG. 4, 5B, 6);
the second outer electrode (22) includes a second plating layer (46) located on the second end surface (back side), and a second charging electrode (45) located on the second end surface (back side) and including a length shorter than a length of the second plating layer (46) in the width direction (see FIG. 4, 5B, 6);
the third outer electrode (24) includes a third plating layer (46) located on the first side surface (left side), and a third charging electrode (45) located on the first side surface (left side) and including a length shorter than a length of the third plating layer (46) in the length direction (see FIG. 4, 5B, 6); and
the fourth outer electrode (23) includes a fourth plating layer (46) located on the second side surface (right side), and a fourth charging electrode (45) located on the second side surface (right side) and including a length shorter than a length of the fourth plating layer (46) in the length direction (see FIG. 4, 5B, 6).
Claim 2
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein
the lengths of the first plating layer (46) and the second plating layer (46) in the width direction are smaller than a length of the multilayer body (20) in the width direction (FIG. 6);
the lengths of the first plating layer (46) and the second plating layer (46) in the lamination direction are smaller than a length of the multilayer body (20) in the lamination direction (FIG. 6: distance d3 is the distance between the bottom surface and the plating layer 46, “Here, in the external ground electrodes 23, 24, the distance d3 between the plating film 46 formed by plating growth on the lead portion 3a of the internal ground conductor 3 and the bottom surface of the multilayer body 20 determines the three-terminal multilayer capacitor 1. It is preferable to set it to half or less of the thickness of the solder paste used when mounting on a printed circuit board”);
the lengths of the third plating layer (46) and the fourth plating layer (46) in the length direction are smaller than the length of the multilayer body (20) in the length direction (FIG. 6); and
lengths of the third plating layer (46) and the fourth plating layer (46) in the lamination direction are smaller than the length of the multilayer body (20) in the lamination direction (FIG. 6: distance d3 is the distance between the bottom surface and the plating layer 46, “Here, in the external ground electrodes 23, 24, the distance d3 between the plating film 46 formed by plating growth on the lead portion 3a of the internal ground conductor 3 and the bottom surface of the multilayer body 20 determines the three-terminal multilayer capacitor 1. It is preferable to set it to half or less of the thickness of the solder paste used when mounting on a printed circuit board”).
Claim 3
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein
the first plating layer (46) and the second plating layer (46) cover the first inner electrode layer (2)(FIG. 6);
the third plating layer (46) and the fourth plating layer (46) cover the second inner electrode layer (3)(FIG. 6, see also FIG. 5B);
the first charging electrode (45) is located on the first plating layer (46) and a surface of the first end surface (front side)(FIG. 6; note that “located on” does not require the charging electrode be located outermost, only that the plating layer and charging electrode are in contact; the claim is not limited to the arrangement shown in application FIG. 4);
the second charging electrode (45) is located on the second plating layer (46) and a surface of the second end surface (back side)(FIG. 6; note that “located on” does not require the charging electrode be located outermost, only that the plating layer and charging electrode are in contact; the claim is not limited to the arrangement shown in application FIG. 4);
the third charging electrode (45) is located on the third plating layer (46) and a surface of the first side surface (left side)(FIG. 5A, 6); and
the fourth charging electrode (45) is located on the fourth plating layer (46) and a surface of the second side surface (right side)(FIG. 5A, 6).
Claim 4
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein
the first charging electrode (45) and the second charging electrode (45) cover the first inner electrode layer (2)(see FIG. 4);
the third charging electrode (45) and the fourth charging electrode (45) cover the second inner electrode layer (3)(see FIG. 4);
the first plating layer (46) is located on the first charging electrode (45) and the first inner electrode layer (2)(see FIG. 6);
the second plating layer (46) is located on the second charging electrode (45) and the first inner electrode layer (2)(see FIG. 6);
the third plating layer (46) is located on the third charging electrode (45) and the second inner electrode layer (3)(see FIG. 6); and
the fourth plating layer (46) is located on the fourth charging electrode (45) and the second inner electrode layer (3)(see FIG. 6).
Claim 5
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein the first charging electrode (45) and the second charging electrode (45) and the third charging electrode (45) and the fourth charging electrode (45) each extend to a portion of the first main surface (top) and a portion of the second main surface (bottom)(FIG. 4).
Claim 8
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein
the first inner electrode layer (2) includes a first opposing electrode portion (body of 2) opposing the second inner electrode layer (3), a first extended electrode portion (2A) extending from the first opposing electrode portion (body of 2) to the first end surface (front side) and a second extended electrode portion (2A) extending from the first opposing electrode portion (body of 2) the second end surface (back side); and
the second inner electrode (3) includes a second opposing electrode portion (body of 3) opposing the first inner electrode layer (2), a third extended electrode portion (3A) extending from the second opposing electrode portion (body of 3) to the first side surface (left side), and a fourth extended electrode portion (3A) extending to the second side surface (right side).
Claim 9
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 8, wherein
the first plating layer (46) directly covers the first extended electrode portion (2A) which is exposed on the first end surface (front side)(see FIG. 4, 6); and
the second plating layer (46) directly covers the second extended electrode portion (3A) which is exposed on the second end surface (back side)(see FIG. 4, 6).
Claim 10
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 4, wherein metal of the first inner electrode layer (2: “These conductors 2 and 3 are made of Ni, Ag, Pd, Cu, Au, alloys thereof, or the like”) and the second inner electrode layer (3: “These conductors 2 and 3 are made of Ni, Ag, Pd, Cu, Au, alloys thereof, or the like”) is diffused into the first plating layer (46, “a Ni and Sn plating film”) through the fourth plating layer (46)(e.g., copper into nickel).
Claim 11
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 4, wherein a thickness of each layer of the first plating layer (46) through the fourth plating layer (46) is about 2 μm or more and about 30 μm or less (“wet plating (electrolytic plating) is performed to form a Ni and Sn plating film having a thickness of about 2 to 15 μm”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of US Publication 2019/0371525 to Zaima et al. (hereinafter Zaima).
Claim 6
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, as shown above.
Matsumoto does not expressly disclose wherein the first plating layer to the fourth plating layer are Cu plating layers, as recited in claim 6 (“wet plating (electrolytic plating) is performed to form a Ni and Sn plating film”).
Zaima (FIG. 9) teaches forming a Cu plating layer (25, 26, paragraph 39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zaima with Matsumoto to incorporate external electrode plating as taught by Zaima in the structure taught by Matsumoto, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for multilayer plating using high conductivity copper for a low resistance interface with the internal electrode, a nickel layer to prevent diffusion, and an outer tin layer for compatibility with solder (Zaima paragraph 39).
Claim 7
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, as shown above.
Matsumoto does not expressly disclose wherein an upper plating layer is located on the first plating layer through the fourth plating layer, and on the first charging electrode through the fourth charging electrode (“wet plating (electrolytic plating) is performed to form a Ni and Sn plating film”).
Zaima (FIG. 9) teaches forming an upper plating layer (27-28) on a lower plating layer (25, 26, paragraph 39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zaima with Matsumoto to incorporate external electrode plating as taught by Zaima in the structure taught by Matsumoto, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for multilayer plating using high conductivity copper for a low resistance interface with the internal electrode, a nickel layer to prevent diffusion, and an outer tin layer for compatibility with solder (Zaima paragraph 39).
Claim 12
Matsumoto discloses the through-type multilayer ceramic capacitor according to claim 1, wherein the first charging electrode (45), the second charging electrode (45), the third charging electrode (45), and the fourth charging electrode (45) are defined by a baked layer including a metal component (“conductive paste 45 mainly containing Cu or the like… is applied to the side surface of the laminated body 20, and then dried, sintered, and fixed”).
Matsumoto does not expressly disclose a baked layer including a glass component and a metal component, as recited in claim 12.
Zaima (FIG. 9) teaches a baked layer (20a) including a glass component and a metal component (paragraph 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zaima with Matsumoto to incorporate glass as taught by Zaima in the baked layer taught by Matsumoto, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for densifying the baked layer (Zaima paragraph 38).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571)270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
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