DETAILED ACTION
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
“first circuitry to receive a command …” in claim 1,
“second circuitry to configure the matrix accelerator …” in claims 1 and 5-8,
“third circuitry to perform operations …” in claim 1
“fourth circuitry to output a result …” in claim 1,
“fifth circuitry to read operands …” in claim 2.
“first circuitry to receive …” in claim 16,
“second circuitry to configure the matrix accelerator …” in claims 16 and 18-20,
“third circuitry to read operands …” in claim 16,
“fourth circuitry to perform operations …” in claim 16,
“fifth circuitry to perform operations …” in claim 16.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon (US 2022/0,138,563).
Referring to claims 1, 9 and 16, Kwon discloses a matrix accelerator (fig. 4, processing hardware; para.0042) comprising:
first circuitry (fig. 4, memory 410) to receive a command (para.0103, commands) to perform operations (fig. 1A, neural network 20 operations) associated with an instruction (paras.0163-0166, instructions);
second circuitry (fig. 4, systolic data setup modules 1/2 420/445) to configure (para.0095, input feature map; para.0100, timing; fig. 1) the matrix accelerator according to a physical depth (fig. 2A, systolic array 240 4x4) of a systolic array (fig. 3A, systolic array 3A) within the matrix accelerator and a logical depth (fig. 2A, NN A 210/NN B 220) associated with the instruction;
third circuitry (fig. 4, systolic array 430) to perform operations (para.0094, deep learning operation) for the instruction via multiple passes (fig. 2A, NN A 210 along time t0/t2 by systolic array 240; para.0039, multitasking) through physical one pipeline stage (fig. 3A, input A 310, input B 320 to array 250) of the systolic array based on a configuration (fig. 5A, systolic data setup 520-1/520-2/545-1/545-2) performed by the second circuitry; and
fourth circuitry to output a result (fig. 4, output accumulators 440) of the operations.
As to claim 2, Kwon discloses the matrix accelerator of claim 1, comprising: fifth circuitry (fig. 4, global buffer 415) to read operands (fig. 1A, input data 10) for the instruction from a memory (fig. 4, main memory 410) associated with the systolic array, wherein the fourth circuitry is to output (fig. 4, output accumulators 440 to memory 410) the result of the operations to the memory associated with the systolic array.
As to claims 3, 11 and 17, Kwon discloses the matrix accelerator of claim 2, wherein the memory associated with the systolic array includes a register file (para.0090, registers).
As to claims 4 and 10, Kwon discloses the matrix accelerator of claim 1, wherein the instruction is a dot product (fig. 1C, convolution operation) instruction.
As to claims 5, 12 and 18, Kwon discloses the matrix accelerator of claim 1, wherein the second circuitry is to configure the systolic array to perform multiple passes (fig. 2A, NN A 210/NN B 220) through the systolic array in response to a determination (fig. 4, systolic data setup 1/2 420/445) that the logical depth associated with the instruction is greater than (fig. 2A, NN A 210/NN B 220 greater than systolic array 240) the physical depth of the systolic array.
As to claims 6, 13 and 19, Kwon discloses the matrix accelerator of claim 5, wherein the second circuitry is to configure the matrix accelerator to perform the multiple passes through the physical pipeline stage of the systolic array as a partial pass (fig. 5A, first area 530) through less than all physical pipeline stages (fig. 5A, first area 530/second area 535) of the systolic array.
As to claims 7 and 14, Kwon discloses the matrix accelerator of claim 6, wherein the second circuitry is to configure the matrix accelerator to power gate (fig. 5A, systolic data setup 520-1 power gate through first area 530) the physical pipeline stage of the systolic array during the partial pass.
As to claims 8, 15 and 20, Kwon discloses the matrix accelerator of claim 7, wherein the second circuitry is to configure the matrix accelerator to bypass and power gate upper physical pipeline stage during the partial pass (fig. 5A, systolic data setup 520-1 power gate through first area 530) and perform the partial pass via lower physical pipeline stages (fig. 5A, perform operations in second area 535).
Response to Arguments
Applicant’s arguments have been fully considered, but they are not deemed to be persuasive.
Applicant argues that Kwon does not disclose “physical depth” and “logical depth” (pp.9-10).
Initially, the requirement for the claim terms “physical depth” and “logical depth” are only limited by what is presented in the claim. There is no specific requirement for them. Therefore, the claim interpretation of the physical depth is a given depth of a physical dimension structure as presented in Kwon. The claim interpretation of the claimed logical depth is a logical depth where an operation utilizes the physical structure.
Applicant argues that the Office action maps the claims to typical technique that Kwon distinguishes, and does not disclose “multiple passes” (pp.10-11).
Once again, applicant is arguing a meaning of claim terms that is not required by the claim. Specifically, the scope of “multiple passes”. For example, what has been passed in which fashion. For example, the meaning of “perform operations for the instruction via multiple passes” does not require the multiple passes being the same pass (e.g., same passage) that is iteratively used. Kwon discloses pipelined operations in clock sequences. The data, such as a11/b11 logically input into the PE array’s physical structure as shown in fig. 4. For example, a possible interpretation would be operations of PE11/PE12/PE13/PE14 for a11/a12/a13/a14/b11/b12/b13/b14 during T1/T2/T3/T4 in multiple passes as shown in fig. 4.
Applicant argues that Kwon does not disclose “partial pass” and “power gate” as claimed (pp.11-12).
Examiner considered an operation that is less than a completion of multiple passes as the claimed partial pass. For example, any operation for a11/a12/a13/a14/b11/b12/b13/b14 operated by PE11/PE12/PE13/PE14 before the entire operation’s completion. Further, examiner interprets the clock cycle and the necessary power that advance data a11/a12/a13/a14 along PE11/PE12/PE13/PE14 as power gating. For example, the operation of each pipelined move of axx/bxx from a PE to next PE is power gated.
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in three months from the mailing date of this action. In the event a first reply is filled within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
