Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 5th, 2026 have been fully considered but they are not persuasive.
On pages 2-3 of the Remarks the Applicants point out that the M4 transistor of Wang performs a different function and is differently connected than the claimed first transistor. While the Office acknowledges these differences Wang is not relied upon to teach the various function and connections as Lin discloses these limitations for the first and second transistors. Rather the proposed combination is merely to form the first and second transistors and capacitor of Lin across first and second layers as taught by Wang.
On page 3 of the Remarks the Applicants argue that Wang fails to disclose forming a storage capacitor in the same first and second layers as the first and second transistors.
The Office respectfully disagrees. Independent claim 1 requires that the storage capacitor “is formed across the first and second layers.” There is no requirement that the entirety of the storage capacitor be included within the first and second layers. Rather the broadest reasonable interpretation of this limitation is seen to only require the inclusion of some portion of the storage capacitor across the first and second layers. Wang discloses the discloses a storage capacitor with a first electrode in layer P4, an insulating layer above the electrode in the P4 layer and a final electrode in layer P5. As such Wang discloses formation of a 2/3rds of the storage capacitor in same first and second layers as the first and second transistor. Should Applicants desire to claim the entire structure of the storage capacitor to be included in the same layers of the transistors, there is simple claim amendments that would further define such an arrangement.
It should be noted that the applicants argue that these above arguments and associated limitations are present in all independent claims. This is incorrect as independent claims 7 and 8 do not include the layer limitations of the storage capacitor.
Finally it is noted that Applicants have noted that the current application has been examined by three and now a fourth examiner. I would agree that this is less than ideal. Recent changes have been implemented by the Office which have resulted in some of the handovers. As much as possible all examiners strive for a consistent and fair examination approach.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, US 2023/0035245, in view of Wang et al(US 20220277691).
Claim 1
Lin (Fig. 3A, 8B) teaches “a display device, comprising:
a base (800);
a plurality of pixels (22) in a matrix along first and second directions intersecting each other in a display area on the base (e.g., Pixels 22 are arranged in a first and second direction in display 14), the first direction being perpendicular to the second direction (e.g., Horizontal(row) and vertical(column) directions, respectively); control signal lines to supply a control signal to the plurality of pixels (e.g., Lines supplying emission signal EM to control the pixels 22); and
power supply lines to supply an initialization voltage to the plurality of pixels (e.g.,
Lines supplying initialization voltage Vini to the pixels 22), wherein
each of the plurality of pixels (22) includes a pixel circuit having a plurality of transistors (Tgd, Tini, Tdrive, Tdata) and a light emitting element (304) drivable by the pixel circuit (e.g., OLED 304 is driven by pixel 22),
the plurality of transistors in the pixel circuit includes a first transistor (Tini) between the power supply line and the light emitting element (e.g., Tini is positioned between the line supplying Vini and OLED 304), the first transistor being controllable based on the control signal (e.g., Tini is controllable by emission signal EM(n)), the control signal lines, which extend to connect to respective sets of pixels of the plurality of pixels arranged in the first direction, are arranged in the second direction (e.g., As shown in Figure 3C, emission driver circuits EM apply emission signals to the pixels through emission lines that are extended in the horizontal direction and are arranged vertically), the power supply lines(VDDEL, VSSEL), which extend to connect to respective sets of pixels of the plurality of pixels(304) arranged in the second direction(vertical direction), are arranged in the first direction(horizontal direction or row direction)(See Figs. 2, 3A; [0041]); a timing at which the control signal is output is different for each of the control signal lines (e.g., As shown in Figure 3D, the emission signal lines EM are output at different timings); the pixel circuit(22) further incudes a storage capacitor (Cst1), the plurality of transistors in the pixel circuit include a second transistor (Tdrive) (e.g., Driving transistor Tdrive provides VDDEL to OLED) configured to supply current to the light emitting element(304)(see Fig. 3; [0040]), the storage capacitor(Cst1) in the pixel circuit(22) is configured to hold a voltage to control the current supplied by the second transistor(Tdrive) to the light emitting element (e.g., Cst1 stores voltages to control Tdrive; see Fig. 3A; [0040, 0043], and the first transistor(Tini) is connected to the storage capacitor (e.g., Tini is connected to bottom terminal of Cst1)(See Fig. 3A; [0040]); the pixel circuit(22) is formed in a circuit layer(802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 823, 825)(see Figs. 8A, 8B, 9; [0081, 0094]) comprised of a first layer(820), a second layer(823), and a third layer(825), the first through third layers are stacked in order with the first layer being a bottom layer of the stack and the third layer being a top layer of the stack(see Fig.9; [0029, [0093, 0094]), the first and second transistors are formed across different layers(see Fig. 9; [0093], and the storage capacitor(CSt1) is formed across the first and second layers(820, 823)(see Fig. 9 and [0094]).
Lin fails to disclose the first and second transistor are formed across the first and second layers.
Wang et al(US 20220277691) teach a display device comprising a first transistor (M4), a second transistor (T) and a storage capacitor (Cst)(See Fig. 2; [0052]), a circuit layer comprising of a first layer (P3), a second layer (P4) and a third layer (P6) are stacked in order(see Figs. 5, 8, 14-17; [081, 0099, 0105, 0106]) . Wang et al teach the first and second transistors are formed across the first and second layers (P3, P4)(see Figs. 8, 14-17; [0088, 0099]), and the storage capacitor (CSt) is formed across the first and second layers (P3, P4)(see Figs. 8, 14-17; [0099]),
Before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify Lin with the above features of Wang et al, since Lin teach the gate of the first and second transistor(Tdrive and Tini) could be different layers or same layer(see Fig. 9 and [0093]), to reduce the thickness, variation and simplify manufacturing.
Claim 3
Lin in view of Wang et al teach the display device of claim 1.
Lin (Figs. 3A, 8B) teaches further comprising:
data signal lines (310) to supply respective data signals to each of the plurality of pixels (e.g., Data lines 310 supply data to the pixels; par. 0045); and
gate signal lines (SCAN1(n), etc.) to supply respective gate signals to each of the plurality of pixels (e.g., Scan lines apply gate signals to the pixels; par. 0036), wherein the plurality of transistors in the pixel circuit include a third transistor controllable based on the gate signal (e.g., Tgd is considered a “third transistor” that is controlled by SCAN1(n)); the data signal lines(310 or 26), which extend to connect to the respective set of pixels(304) arranged in the second direction(vertical direction), are arranged in the first direction (e.g., Data signal lines DL are arranged horizontally)(see Figs. 2, 3A, [0038]) and
the gate signal lines(314 or 28), which extend to connect to the respective set of pixels(304) arranged in the first direction(horizontal(row) direction), are arranged in the second direction (vertical(column) direction)(see Figs. 2-3A; [0038, 0052]).”
Claim 4
Lin in view of Wang et al teach the display device of claim 3.
Lin (Figs. 3A, 8B) further teaches “wherein in each of the plurality of pixels, the data signal is written to each of the plurality of pixels arranged in the first direction (e.g., Data signal D is applied to data line 310; par. 0045), and the first transistor becomes an on state based on the control signal.”
Claim 7
See claim 1 rejection above.
Lin fails to disclose the control signal lines are formed on the second layer and
data line is formed on the third layer.
Wang et al teach a display device comprising a pixel driving circuit(10)(see Fig. 2
) having the control signal lines(Emit) are formed on the second layer(P4)(see Figs.
2, 5, 8 [0052]) and a data line(Data) is formed on the third layer(P6)(see Figs. 2, 5, 8,
[0052, 0080-0081]). Before the effective filing date of the invention, it would have
been obvious to one with ordinary skill in the art to modify Lin with the above
features of Wang et al, so as to reduce the thickness, variation and simplify
manufacturing.
Claim 8
See claim 1 rejection above.
Lin fails to disclose the control signal lines are formed on the second layer.
Wang et al teach a display device comprising the control signal lines(Emit) are
formed on the second layer(P4)(see Figs. 2, 8; [0052]). Before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify Lin with the above features of Wang et al, so as to reduce the thickness, variation and simplify manufacturing.
Claim 9
Lin teaches a display device comprising the pixel circuit further includes a
storage capacitor(Cst1), the storage capacitor in the pixel circuit is configured to
hold a voltage to control the current supplied by the second transistor(Tdrive) to
the light emitting element(304)(see Fig. 3A; [0040, 0043]), and the first
transistor(Tini) is connected to the storage capacitor(Cst1)(see Fig. 3A; [0040]).
Claim 10
Lin teaches a display device comprising: data signal lines(310 or 26) to supply
respective data signals to each of the plurality of pixels(304 or 22)(see Figs. 2, 3A;
[0039]); and gate signal lines(314 or 28) to supply respective gate signals to each
of the plurality of pixels(304 or 22)(see Figs. 2, 3A; [0039, 0042]), wherein the
plurality of transistors in the pixel circuit include a third transistor(Tdata)
controllable based on the gate signal(314 or 28), the data signal lines(310 or Data),
which extend to connect to the respective set of pixels(304 or 22) arranged in the
second direction(vertical(column) direction), are arranged in the first
direction(horizontal(row) direction)(see Figs. 2, 3A; [0039, 0045]), and
the gate signal lines(314 or 28), which extend to connect to the respective set of
pixels(304 or 22) arranged in the first direction(horizontal(row) direction), are
arranged in the second direction(vertical(column) direction)(see Figs. 2-3A; [0038, 0052]).
Claim 11
Lin fails to disclose the storage capacitor is formed across the first and second layers,
the gate signal lines are formed on the second layer and data line is formed on the
third layer.
Wang et al teach a display device comprising the storage capacitor(Cst) is
formed across the first and second layers (P3, P4)(see Figs. 14-17; [0099]),
the gate signal lines(Scan2) are formed on the second layer(P4)(see Fig. 25;
[0126]) , and the data signal lines(Data) are formed on the third layer(P6)(see Figs.
2, 5, [0052, 0080-0081]). Before the effective filing date of the invention, it
would have been obvious to one with ordinary skill in the art to modify Lin with
the above features of Wang et al, so as to reduce the thickness, variation and
simplify manufacturing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chai et al(US 20240196680) teach a display device comprising a pixel circuit having a driving transistor(T3), a compensation transistor(T4) and storage capacitor(C) across a first and second layer(M1, M2)(see Figs. 2, 4; [0055]).
Chai et al(US 20240164162) teach a display device comprising a pixel circuit having a first transistor(Tm), a second transistor(M3) and storage capacitor(Cst) across a first and second layer(02, 03)(see Figs. 2, 4, [0041, 0043]).
Yang(US 20240049529) teach a display device comprising a pixel circuit having a first transistor(T1), a second transistor(T2) and a storage capacitor(CL) are formed on a driving array(102)(see Figs. 2B, 3; [0043]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William L Boddie whose telephone number is (571)272-0666. The examiner can normally be reached 8 - 4:15 M-F.
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/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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