CTNF 18/931,734 CTNF 74491 Detailed Office Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 – 4, 9 – 21 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Pentakota et al. (US Patent Number 11,316,525) . Regarding claim 1, Pentakota et al. disclose a system (figs. 1, 3) comprising: a first analog-to-digital converter (ADC) (18) having an output; a look-up table (LUT) (20, fig. 1,3; paragraphs bridging col. 2 and 3) having an input and an output, the input of LUT is coupled to the output of the first ADC (figs. 1, 3); a second ADC (10, fig. 3) having an output; and a calibration circuitry (30) coupled to the output of the LUT and to the output of the second ADC. PNG media_image1.png 748 657 media_image1.png Greyscale Regarding claim 2, Pentakota et al. disclose a system (figs. 1, 3), wherein the calibration circuitry (30) is configured to provide an error signal to the LUT and a trigger signal to the second ADC (col. 2, line 61 to col. 3 , line 25). Regarding claim 3, Pentakota et al. disclose a system (figs. 1, 3), wherein the first ADC (18) is a first type ADC and the second ADC (10) is a second type ADC different from the first type ADC (col. 2, line 61 to col. 3 , line 25). Regarding claim 4, Pentakota et al. disclose a system (figs. 1, 3), wherein the first ADC (18) is a non-linear ADC and the second ADC (10)is a linear ADC (col. 2, line 61 to col. 3 , line 25). Regarding claim 9, Pentakota et al. disclose a method (figs. 1, 3) comprising: storing, in a look-up table (LUT) (20) , output codes generated by a first analog-to-digital converter (ADC) corresponding to digital codes received by a DAC (figs. 1,3; paragraphs bridging col. 2 and 3); determining an error between a first signal path and a second signal path , the first ADC (18) coupled to an output of the first signal path and a second ADC (10) coupled to an output of the second signal path; and updating the LUT based on the error between the first signal path and the second signal path (abstract; (figs. 1, 3; paragraphs bridging col. 2 and 3). Regarding claim 10, Pentakota et al. disclose a method (figs. 1, 3), wherein determining the error between the first signal path and the second signal path further comprising: determining a linear error between the first signal path and the second signal path (fig. 1,3; paragraphs bridging col. 2 and 3); and determining a non-linear error between the first signal path and the second signal path based at least in part on the linear error (fig. 1,3; paragraphs bridging col. 2 and 3). Regarding claim 11, Pentakota et al. disclose a method (figs. 1, 3), wherein determining the linear error further comprising determining gain of the second signal path (figs. 1, 3; paragraphs bridging col. 2 and 3). Regarding claim 12 , Pentakota et al. disclose a method (figs. 1, 3), wherein determining the linear error further comprising determining previous output signal on the first signal path and a time derivative of a current output signal on the first signal path (figs. 1,3; paragraphs bridging col. 2 and 3). Regarding claim 13, Pentakota et al. disclose a method (figs. 1, 2),, wherein determining the non-linear error using a basis-spline function (fig. 1,2; paragraphs bridging col. 2 and 3). Regarding claim 14, Pentakota et al. disclose a method (figs. 1, 2), further comprising operating the first ADC (18) as a non-linear ADC and operating the second ADC (10) as a linear ADC. Regarding claim 15, Pentakota et al. disclose analog to digital converter (figs. 1, 3) comprising: a calibration path having a digital to analog converter (DAC) and a first voltage to delay converter (V2D) (V1) (fig. 3); a first signal path having a second voltage to delay converter (V2D) (V2); a first multiplexer (12) coupled to the calibration path and the first signal path (figs. 1, 3); a first analog-to-digital converter (ADC) (18) coupled to the multiplexer; a second signal path having a second analog-to-digital converter (ADC) (10), a look-up table (LUT) (20) coupled to the first ADC (18); and a calibration circuitry (30) coupled to the LUT and to the second ADC (fig. 3). Regarding claim 16, Pentakota et al. disclose analog to digital converter (figs. 1, 3), wherein the calibration circuitry (30) is coupled to an output of the LUT (20) and to an output of the second ADC (fig. 3), and the calibration circuitry is configured to provide an error signal to the LUT and a trigger signal to the second ADC (fig. 3). Regarding claim 17, Pentakota et al. disclose analog to digital converter (figs. 1, 3), wherein the first ADC (18) is a non-linear ADC and the second ADC (10)is a linear ADC. Regarding claim 18, Pentakota et al. disclose analog to digital converter (figs. 1, 3), wherein the first V2D (V1) having an input and an output, the input of the first V2D coupled to the DAC (32) and the output of the first V2D coupled to a first input of the first multiplexer (12, figs. 1, 3). Regarding claim 19, Pentakota et al. disclose analog to digital converter (figs. 1, 3) wherein the second V2D (V2) having an input and an output, the input of the second V2D configured to receive an input signal and the output of the second V2D coupled to a second input of the first multiplexer (see figs. 1, 3). Regarding claim 20, Pentakota et al. disclose analog to digital converter (figs. 1, 3), herein the second signal path further comprises: an attenuator configured to receive the input signal (figs. 1, 3); and a second multiplexer(14, figs. 1, 3) having an input and an output, the output of the second multiplexer coupled to the second ADC and the input of the second multiplexer coupled to the attenuator (figs. 3). Regarding claim 21, Pentakota et al. disclose analog to digital converter (figs. 1, 3), wherein the LUT (20) is configured to map an output of the first ADC to a DAC code . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5 - 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845 Application/Control Number: 18/931,734 Page 2 Art Unit: 2845 Application/Control Number: 18/931,734 Page 3 Art Unit: 2845 Application/Control Number: 18/931,734 Page 4 Art Unit: 2845 Application/Control Number: 18/931,734 Page 5 Art Unit: 2845 Application/Control Number: 18/931,734 Page 6 Art Unit: 2845 Application/Control Number: 18/931,734 Page 7 Art Unit: 2845
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